From patchwork Tue Oct 16 09:15:50 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 191757 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 01CFE2C0097 for ; Tue, 16 Oct 2012 20:16:36 +1100 (EST) Received: from localhost ([::1]:43143 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3GM-00065L-4H for incoming@patchwork.ozlabs.org; Tue, 16 Oct 2012 05:16:34 -0400 Received: from eggs.gnu.org ([208.118.235.92]:56818) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3GB-000659-Bx for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:16:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TO3G1-0004LE-Jd for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:16:23 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:64951) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TO3G1-0004KB-DE for qemu-devel@nongnu.org; Tue, 16 Oct 2012 05:16:13 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so5672387pad.4 for ; Tue, 16 Oct 2012 02:16:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=mpx+Vx00JroYMV2JjMy7tZxJsk40qrKUjZ9Z/7SCG5M=; b=gOyNwh5PNxLbuN1kfEaDqSwzXyIyi4dkTqAr1UsVJOgP1gyFEq1v8t+nV1e+5YmuJY EqEca70fPBCEvqChYeO+oBQbpO7+BA4+NHin3N9Vqj3gqa/fVMe07x+KHQE+rtOnOCSP O8MtKtnLA3QsbJgqAObYKHZ+vFUg/jp+SWRnpPwZplIAnKvzBVNpk4AKGGjNE4e87ccp Ws0uEK1r8rsnxWMgSKWwjAUPX/muAXKnlZv4jOvf/LZfF3kqesjb+vQ1v1z6Vbm9yI3S WT5XOoYEE3LuOMnaxhQ2JbdOaGN35NzPxBX6uAl3aBtVd/YFDUCorpdzMLQYnZR8zMOF VP8g== Received: by 10.68.248.10 with SMTP id yi10mr44962749pbc.39.1350378971082; Tue, 16 Oct 2012 02:16:11 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id sa2sm10502842pbc.4.2012.10.16.02.16.08 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 16 Oct 2012 02:16:10 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, peter.maydell@linaro.org Date: Tue, 16 Oct 2012 19:15:50 +1000 Message-Id: <1350378950-10614-1-git-send-email-peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 X-Gm-Message-State: ALoCoQljqSumtcHSmELLAdDU4/qtQCwFc5B2OrmQagWAPXMUkldCe8mGc5HC0rvMuJ3x3e+krA5l X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: Peter Crosthwaite Subject: [Qemu-devel] [PATCH] target-arm/translate: Fix RRX operands X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Instructions that both use the RRX second operand and update CS were incorrect, as the Carry flag was updated too early. An example of such an instruction would be: ands r12,r13,RRX Ands, because of the "s" flag will update the carry flag. But the RRX second operand rotates through the C flag which should happen before the update. Fixed the ordering of the two, the old carry is read by "r13,RRX" before being updated. Signed-off-by: Peter Crosthwaite Reported-by: Vinesh Peringat Reviewed-by: Peter Maydell --- target-arm/translate.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index c6840b7..daccb15 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -516,10 +516,10 @@ static inline void gen_arm_shift_im(TCGv var, int shiftop, int shift, int flags) tcg_gen_rotri_i32(var, var, shift); break; } else { TCGv tmp = tcg_temp_new_i32(); + tcg_gen_shli_i32(tmp, cpu_CF, 31); if (flags) shifter_out_im(var, 0); tcg_gen_shri_i32(var, var, 1); - tcg_gen_shli_i32(tmp, cpu_CF, 31); tcg_gen_or_i32(var, var, tmp); tcg_temp_free_i32(tmp); }