From patchwork Mon Oct 15 16:39:09 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jia Liu X-Patchwork-Id: 191600 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 9DB652C00A7 for ; Tue, 16 Oct 2012 04:00:44 +1100 (EST) Received: from localhost ([::1]:34863 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TNniz-0000ag-4K for incoming@patchwork.ozlabs.org; Mon, 15 Oct 2012 12:41:05 -0400 Received: from eggs.gnu.org ([208.118.235.92]:35097) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TNniS-0007fe-Rj for qemu-devel@nongnu.org; Mon, 15 Oct 2012 12:40:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TNniO-0006Rj-HO for qemu-devel@nongnu.org; Mon, 15 Oct 2012 12:40:32 -0400 Received: from mail-da0-f45.google.com ([209.85.210.45]:62016) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TNniO-0006Qn-Az for qemu-devel@nongnu.org; Mon, 15 Oct 2012 12:40:28 -0400 Received: by mail-da0-f45.google.com with SMTP id n15so2658891dad.4 for ; Mon, 15 Oct 2012 09:40:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :content-type; bh=LcABi5m/XlUdkITYCJS5ELSo2Aw1k6XqxDofV+QdJUo=; b=tj8q2E20EQoilyPZaO67GtnIFlccTR1E7Iz2WSSCNnDctdW8ZY0iig343Cahs7BA2S jzQKH7m1py/Bh4wwV6WfiA+Qu16mWC+RKkjy0GhX0cKsRX2Dn5mDV86f3zN+D3Sx6w2J S5miMJVnL6qYt/v4HkH0bvtAYL0xNR0JRcEy5TLHgJgL5TaxffoXT6Y8rt7/O8CjR4g3 COf2LGKLeSzXqG0Fka0xH4C8ePMvQdd+pHZ+N25nIFYp2/Cxx2Y51d3oq5vLRp+uY94u hfJLBp7YeBt/1+aOHFBT2iIfEtLotc3HJTedooS+flBDJl+LuFnL3tkOYA4t37pxVYgX cDgQ== Received: by 10.66.73.6 with SMTP id h6mr34353456pav.69.1350319227503; Mon, 15 Oct 2012 09:40:27 -0700 (PDT) Received: from localhost.localdomain ([123.150.196.81]) by mx.google.com with ESMTPS id ka4sm9289654pbc.61.2012.10.15.09.40.17 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 15 Oct 2012 09:40:26 -0700 (PDT) From: Jia Liu To: qemu-devel@nongnu.org Date: Tue, 16 Oct 2012 00:39:09 +0800 Message-Id: <1350319158-7263-6-git-send-email-proljc@gmail.com> X-Mailer: git-send-email 1.7.10.2 (Apple Git-33) In-Reply-To: <1350319158-7263-1-git-send-email-proljc@gmail.com> References: <1350319158-7263-1-git-send-email-proljc@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.210.45 Cc: aurelien@aurel32.net Subject: [Qemu-devel] [PATCH v11 05/14] target-mips: Add ASE DSP load instructions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu --- target-mips/translate.c | 89 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index f1e5bb0..7f08700 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -313,6 +313,9 @@ enum { OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, + + /* MIPS DSP Load */ + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, }; /* BSHFL opcodes */ @@ -340,6 +343,17 @@ enum { #endif }; +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +/* MIPS DSP Load */ +enum { + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, +#if defined(TARGET_MIPS64) + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -12213,6 +12227,64 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b #endif +/* MIPSDSP functions. */ +static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rd, int base, int offset) +{ + const char *opn = "ldx"; + TCGv t0 = tcg_temp_new(); + + if (rd == 0 && env->insn_flags & (ASE_DSP | ASE_DSPR2)) { + MIPS_DEBUG("NOP"); + return; + } else if (base == 0) { + if (offset == 0) { + /* Address error. */ + generate_exception(ctx, EXCP_AdEL); + } else { + gen_load_gpr(t0, offset); + } + } else if (offset == 0) { + gen_load_gpr(t0, base); + } else { + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); + save_cpu_state(ctx, 0); + } + + check_dsp(ctx); + switch (opc) { + case OPC_LBUX: + op_ld_lbu(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lbux"; + break; + case OPC_LHX: + op_ld_lh(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lhx"; + break; + case OPC_LWX: + op_ld_lw(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lwx"; + break; +#if defined(TARGET_MIPS64) + case OPC_LDX: + op_ld_ld(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "ldx"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s(%s)", opn, + regnames[rd], regnames[offset], regnames[base]); + tcg_temp_free(t0); +} + + +/* End MIPSDSP functions. */ + static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) { int32_t offset; @@ -12569,6 +12641,23 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + case OPC_LX_DSP: + op2 = MASK_LX(ctx->opcode); + switch (op2) { +#if defined(TARGET_MIPS64) + case OPC_LDX: +#endif + case OPC_LBUX: + case OPC_LHX: + case OPC_LWX: + gen_mipsdsp_ld(env, ctx, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK LX"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: