From patchwork Mon Oct 15 15:37:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 191572 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 7D9932C00A8 for ; Tue, 16 Oct 2012 02:37:55 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A302F4A09F; Mon, 15 Oct 2012 17:37:47 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id paZuJnWD+024; Mon, 15 Oct 2012 17:37:47 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3399B4A088; Mon, 15 Oct 2012 17:37:45 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 124834A088 for ; Mon, 15 Oct 2012 17:37:43 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id pbJ9FzLuOpwm for ; Mon, 15 Oct 2012 17:37:40 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from am1outboundpool.messaging.microsoft.com (am1ehsobe006.messaging.microsoft.com [213.199.154.209]) by theia.denx.de (Postfix) with ESMTPS id 01F3E4A050 for ; Mon, 15 Oct 2012 17:37:37 +0200 (CEST) Received: from mail77-am1-R.bigfish.com (10.3.201.248) by AM1EHSOBE009.bigfish.com (10.3.204.29) with Microsoft SMTP Server id 14.1.225.23; Mon, 15 Oct 2012 15:37:35 +0000 Received: from mail77-am1 (localhost [127.0.0.1]) by mail77-am1-R.bigfish.com (Postfix) with ESMTP id 895DD360118; Mon, 15 Oct 2012 15:37:35 +0000 (UTC) X-Forefront-Antispam-Report: CIP:70.37.183.190; KIP:(null); UIP:(null); IPV:NLI; H:mail.freescale.net; RD:none; EFVD:NLI X-SpamScore: 0 X-BigFish: VS0(zzzz1202h1d1ah1d2ahzz8275bhz2dh2a8h668h839hd24he5bhf0ah107ah1288h12a5h12a9h12bdh12e5h137ah139eh13b6h1441h1155h) Received: from mail77-am1 (localhost.localdomain [127.0.0.1]) by mail77-am1 (MessageSwitch) id 1350315453351347_11386; Mon, 15 Oct 2012 15:37:33 +0000 (UTC) Received: from AM1EHSMHS014.bigfish.com (unknown [10.3.201.246]) by mail77-am1.bigfish.com (Postfix) with ESMTP id 4F9B21C0078; Mon, 15 Oct 2012 15:37:33 +0000 (UTC) Received: from mail.freescale.net (70.37.183.190) by AM1EHSMHS014.bigfish.com (10.3.207.152) with Microsoft SMTP Server (TLS) id 14.1.225.23; Mon, 15 Oct 2012 15:37:32 +0000 Received: from az84smr01.freescale.net (10.64.34.197) by 039-SN1MMR1-002.039d.mgd.msft.net (10.84.1.15) with Microsoft SMTP Server (TLS) id 14.2.309.3; Mon, 15 Oct 2012 15:37:30 +0000 Received: from fabio-Latitude-E6410.am.freescale.net ([10.29.240.141]) by az84smr01.freescale.net (8.14.3/8.14.0) with ESMTP id q9FFbKmq009810; Mon, 15 Oct 2012 08:37:23 -0700 From: Fabio Estevam To: Date: Mon, 15 Oct 2012 12:37:15 -0300 Message-ID: <1350315437-29848-1-git-send-email-fabio.estevam@freescale.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-OriginatorOrg: freescale.com Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 1/3] mx5: lowlevel_init.S: Split init_clock macro X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de init_clock is currently shared between mx51 and mx53 and it contains lots of ifdef's which makes it really hard to follow the code. Split the init_clock between mx51 and mx53 to allow easier readability. No functional changes are made. Signed-off-by: Fabio Estevam --- arch/arm/cpu/armv7/mx5/lowlevel_init.S | 95 ++++++++++++++++++++++---------- 1 file changed, 65 insertions(+), 30 deletions(-) diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 529e35b..d0bab45 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -162,9 +162,9 @@ setup_pll_func: .endm .macro init_clock +#if defined (CONFIG_MX51) ldr r0, =CCM_BASE_ADDR -#if defined(CONFIG_MX51) /* Gate of clocks to the peripherals first */ ldr r1, =0x3FFFFFFF str r1, [r0, #CLKCTL_CCGR0] @@ -190,21 +190,6 @@ setup_pll_func: 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 bne 1b -#else - ldr r1, =0x3FFFFFFF - str r1, [r0, #CLKCTL_CCGR0] - str r4, [r0, #CLKCTL_CCGR1] - str r4, [r0, #CLKCTL_CCGR2] - str r4, [r0, #CLKCTL_CCGR3] - str r4, [r0, #CLKCTL_CCGR7] - - ldr r1, =0x00030000 - str r1, [r0, #CLKCTL_CCGR4] - ldr r1, =0x00FFF030 - str r1, [r0, #CLKCTL_CCGR5] - ldr r1, =0x0F00030F - str r1, [r0, #CLKCTL_CCGR6] -#endif /* Switch ARM to step clock */ mov r1, #0x4 @@ -217,7 +202,6 @@ setup_pll_func: setup_pll PLL1_BASE_ADDR, 800 #endif -#if defined(CONFIG_MX51) setup_pll PLL3_BASE_ADDR, 665 /* Switch peripheral to PLL 3 */ @@ -234,7 +218,7 @@ setup_pll_func: str r1, [r0, #CLKCTL_CBCDR] ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL str r1, [r0, #CLKCTL_CBCMR] -#endif + setup_pll PLL3_BASE_ADDR, 216 /* Set the platform clock dividers */ @@ -244,21 +228,17 @@ setup_pll_func: ldr r0, =CCM_BASE_ADDR -#if defined(CONFIG_MX51) /* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */ ldr r3, [r4, #ROM_SI_REV] cmp r3, #0x10 movls r1, #0x1 movhi r1, #0 -#else - mov r1, #0 -#endif + str r1, [r0, #CLKCTL_CACRR] /* Switch ARM back to PLL 1 */ str r4, [r0, #CLKCTL_CCSR] -#if defined(CONFIG_MX51) /* setup the rest */ /* Use lp_apm (24MHz) source for perclk */ ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL @@ -266,7 +246,6 @@ setup_pll_func: /* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */ ldr r1, =CONFIG_SYS_CLKTL_CBCDR str r1, [r0, #CLKCTL_CBCDR] -#endif /* Restore the default values in the Gate registers */ ldr r1, =0xFFFFFFFF @@ -277,17 +256,72 @@ setup_pll_func: str r1, [r0, #CLKCTL_CCGR4] str r1, [r0, #CLKCTL_CCGR5] str r1, [r0, #CLKCTL_CCGR6] -#if defined(CONFIG_MX53) - str r1, [r0, #CLKCTL_CCGR7] -#endif -#if defined(CONFIG_MX51) /* Use PLL 2 for UART's, get 66.5MHz from it */ ldr r1, =0xA5A2A020 str r1, [r0, #CLKCTL_CSCMR1] ldr r1, =0x00C30321 str r1, [r0, #CLKCTL_CSCDR1] -#elif defined(CONFIG_MX53) + /* make sure divider effective */ +1: ldr r1, [r0, #CLKCTL_CDHIPR] + cmp r1, #0x0 + bne 1b + + str r4, [r0, #CLKCTL_CCDR] + + /* for cko - for ARM div by 8 */ + mov r1, #0x000A0000 + add r1, r1, #0x00000F0 + str r1, [r0, #CLKCTL_CCOSR] +#else /* CONFIG_MX53 */ + ldr r0, =CCM_BASE_ADDR + + /* Gate of clocks to the peripherals first */ + ldr r1, =0x3FFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r4, [r0, #CLKCTL_CCGR1] + str r4, [r0, #CLKCTL_CCGR2] + str r4, [r0, #CLKCTL_CCGR3] + str r4, [r0, #CLKCTL_CCGR7] + ldr r1, =0x00030000 + str r1, [r0, #CLKCTL_CCGR4] + ldr r1, =0x00FFF030 + str r1, [r0, #CLKCTL_CCGR5] + ldr r1, =0x0F00030F + str r1, [r0, #CLKCTL_CCGR6] + + /* Switch ARM to step clock */ + mov r1, #0x4 + str r1, [r0, #CLKCTL_CCSR] + + setup_pll PLL1_BASE_ADDR, 800 + + setup_pll PLL3_BASE_ADDR, 216 + + /* Set the platform clock dividers */ + ldr r0, =ARM_BASE_ADDR + ldr r1, =0x00000725 + str r1, [r0, #0x14] + + ldr r0, =CCM_BASE_ADDR + + mov r1, #0 + str r1, [r0, #CLKCTL_CACRR] + + /* Switch ARM back to PLL 1 */ + str r4, [r0, #CLKCTL_CCSR] + + /* Restore the default values in the Gate registers */ + ldr r1, =0xFFFFFFFF + str r1, [r0, #CLKCTL_CCGR0] + str r1, [r0, #CLKCTL_CCGR1] + str r1, [r0, #CLKCTL_CCGR2] + str r1, [r0, #CLKCTL_CCGR3] + str r1, [r0, #CLKCTL_CCGR4] + str r1, [r0, #CLKCTL_CCGR5] + str r1, [r0, #CLKCTL_CCGR6] + str r1, [r0, #CLKCTL_CCGR7] + /* Switch peripheral to PLL2 */ ldr r0, =CCM_BASE_ADDR ldr r1, =0x00808145 @@ -306,7 +340,7 @@ setup_pll_func: and r1, r1, #0xffffffc0 orr r1, r1, #0x0a str r1, [r0, #CLKCTL_CSCDR1] -#endif + /* make sure divider effective */ 1: ldr r1, [r0, #CLKCTL_CDHIPR] cmp r1, #0x0 @@ -318,6 +352,7 @@ setup_pll_func: mov r1, #0x000A0000 add r1, r1, #0x00000F0 str r1, [r0, #CLKCTL_CCOSR] +#endif /* CONFIG_MX53 */ .endm .macro setup_wdog