From patchwork Sat Oct 13 08:38:59 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 191286 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id D21322C0089 for ; Sat, 13 Oct 2012 19:39:12 +1100 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:MIME-Version:Received:Received:Date:Message-ID:Subject:From:To:Content-Type:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=LREmyutmzPZHwojfjT9iPUa1aITR6E0pMrjp0hrr0/b1+s21Hdx4W3lyN9ou7H 676MBuUQ1ib5DzqZVHwsHwaVakazIJ3rppCkYYUYNgSM6FNvJ2gOr7bNsrnfWmX9 U8l+z0Ibfgbdj8ESX77+RfnxpwvxrV5FIEFn2JfozZtXk=; Received: (qmail 12244 invoked by alias); 13 Oct 2012 08:39:08 -0000 Received: (qmail 12236 invoked by uid 22791); 13 Oct 2012 08:39:07 -0000 X-SWARE-Spam-Status: No, hits=-0.1 required=5.0 tests=AWL, BAYES_50, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, KHOP_RCVD_TRUST, MEDICAL_SUBJECT, RCVD_IN_DNSWL_LOW, RCVD_IN_HOSTKARMA_YE, TW_FP, TW_TQ, TW_VT, TW_ZJ X-Spam-Check-By: sourceware.org Received: from mail-da0-f47.google.com (HELO mail-da0-f47.google.com) (209.85.210.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 13 Oct 2012 08:39:00 +0000 Received: by mail-da0-f47.google.com with SMTP id s35so1711504dak.20 for ; Sat, 13 Oct 2012 01:39:00 -0700 (PDT) MIME-Version: 1.0 Received: by 10.68.225.34 with SMTP id rh2mr20535211pbc.78.1350117539985; Sat, 13 Oct 2012 01:38:59 -0700 (PDT) Received: by 10.66.246.232 with HTTP; Sat, 13 Oct 2012 01:38:59 -0700 (PDT) Date: Sat, 13 Oct 2012 10:38:59 +0200 Message-ID: Subject: [PATCH, alpha]: Trivial alpha.md macroizations, part 4 From: Uros Bizjak To: gcc-patches@gcc.gnu.org Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hello! 2012-10-13 Uros Bizjak * config/alpha/alpha.md (FMODE): New mode iterator. (modesuffix): Handle SF and DF modes. (opmode): New mode attribute. (abs2): Macroize insn from abs{sf,df}2 using FMODE mode iterator. (*nabs2): Macroize insn from *nabs{sf,df}2 using FMODE mode iterator. (neg2): Macroize insn from neg{sf,df}2 using FMODE mode iterator. (copysign3): Macroize insn from copysign{sf,df}3 using FMODE mode iterator. (*ncopysign3): Macroize insn from *ncopysign{sf,df}3 using FMODE mode iterator. (*add3_ieee): Macroize insn from *add{sf,df}_ieee using FMODE mode iterator. (add3): Macroize insn from add{sf,df}3 using FMODE mode iterator. (*sub3_ieee): Macroize insn from *sub{sf,df}3_ieee using FMODE mode iterator. (sub3): Macroize insn from sub{sf,df}3 using FMODE mode iterator. (*mul3_ieee): Macroize insn from *mul{sf,df}3_ieee using FMODE mode iterator. (mul3): Macroize insn from mul{sf,df}3 using FMODE mode iterator. (*div3_ieee): Macroize insn from *div{sf,df}3_ieee using FMODE mode iterator. (div3): Macroize insn from div{sf,df}3 using FMODE mode iterator. (*sqrt2_ieee): Macroize insn from *sqrt{sf,df}2_ieee using FMODE mode iterator. (sqrt2): Macroize insn from sqrt{sf,df}2 using FMODE mode iterator. (*movcc_internal): Macroize insn from *mov{sf,df}cc_internal using FMODE mode iterator. (movcc): Macroize expander from mov{sf,df}cc using FMODE mode iterator. Tested on alphaev68-linux-gnu, committed to mainline SVN. Uros. Index: config/alpha/alpha.md =================================================================== --- config/alpha/alpha.md (revision 192396) +++ config/alpha/alpha.md (working copy) @@ -98,7 +98,8 @@ (define_mode_attr DWI [(SI "DI") (DI "TI")]) (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") - (V8QI "b8") (V4HI "w4")]) + (V8QI "b8") (V4HI "w4") + (SF "%,") (DF "%-")]) (define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) (define_code_iterator any_maxmin [smax smin umax umin]) @@ -1666,30 +1667,21 @@ ;; from single, so indicate that. The exception are the ones that simply ;; play with the sign bits; it's not clear what to do there. -(define_insn "abssf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "cpys $f31,%R1,%0" - [(set_attr "type" "fcpys")]) +(define_mode_iterator FMODE [SF DF]) -(define_insn "*nabssf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (abs:SF (match_operand:SF 1 "reg_or_0_operand" "fG"))))] - "TARGET_FP" - "cpysn $f31,%R1,%0" - [(set_attr "type" "fadd")]) +(define_mode_attr opmode [(SF "si") (DF "di")]) -(define_insn "absdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] +(define_insn "abs2" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] "TARGET_FP" "cpys $f31,%R1,%0" [(set_attr "type" "fcpys")]) -(define_insn "*nabsdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (abs:DF (match_operand:DF 1 "reg_or_0_operand" "fG"))))] +(define_insn "*nabs2" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (neg:FMODE + (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))] "TARGET_FP" "cpysn $f31,%R1,%0" [(set_attr "type" "fadd")]) @@ -1717,20 +1709,13 @@ [(const_int 0)] "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") -(define_insn "negsf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] +(define_insn "neg2" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] "TARGET_FP" "cpysn %R1,%R1,%0" [(set_attr "type" "fadd")]) -(define_insn "negdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "cpysn %R1,%R1,%0" - [(set_attr "type" "fadd")]) - (define_expand "negtf2" [(parallel [(set (match_operand:TF 0 "register_operand" "") (neg:TF (match_operand:TF 1 "reg_or_0_operand" ""))) @@ -1754,118 +1739,286 @@ [(const_int 0)] "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") -(define_insn "copysignsf3" - [(set (match_operand:SF 0 "register_operand" "=f") - (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")] - UNSPEC_COPYSIGN))] +(define_insn "copysign3" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")] + UNSPEC_COPYSIGN))] "TARGET_FP" "cpys %R2,%R1,%0" [(set_attr "type" "fadd")]) -(define_insn "*ncopysignsf3" - [(set (match_operand:SF 0 "register_operand" "=f") - (neg:SF (unspec:SF [(match_operand:SF 1 "reg_or_0_operand" "fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")] - UNSPEC_COPYSIGN)))] +(define_insn "*ncopysign3" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (neg:FMODE + (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")] + UNSPEC_COPYSIGN)))] "TARGET_FP" "cpysn %R2,%R1,%0" [(set_attr "type" "fadd")]) -(define_insn "copysigndf3" - [(set (match_operand:DF 0 "register_operand" "=f") - (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")] - UNSPEC_COPYSIGN))] +(define_insn "*add3_ieee" + [(set (match_operand:FMODE 0 "register_operand" "=&f") + (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] + "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" + "add%/ %R1,%R2,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_insn "add3" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] "TARGET_FP" - "cpys %R2,%R1,%0" - [(set_attr "type" "fadd")]) + "add%/ %R1,%R2,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) -(define_insn "*ncopysigndf3" +(define_insn "*adddf_ext1" [(set (match_operand:DF 0 "register_operand" "=f") - (neg:DF (unspec:DF [(match_operand:DF 1 "reg_or_0_operand" "fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")] - UNSPEC_COPYSIGN)))] - "TARGET_FP" - "cpysn %R2,%R1,%0" - [(set_attr "type" "fadd")]) + (plus:DF (float_extend:DF + (match_operand:SF 1 "reg_or_0_operand" "fG")) + (match_operand:DF 2 "reg_or_0_operand" "fG")))] + "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" + "add%-%/ %R1,%R2,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) -(define_insn "*addsf_ieee" - [(set (match_operand:SF 0 "register_operand" "=&f") - (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")))] +(define_insn "*adddf_ext2" + [(set (match_operand:DF 0 "register_operand" "=f") + (plus:DF (float_extend:DF + (match_operand:SF 1 "reg_or_0_operand" "%fG")) + (float_extend:DF + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] + "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" + "add%-%/ %R1,%R2,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_expand "addtf3" + [(use (match_operand:TF 0 "register_operand" "")) + (use (match_operand:TF 1 "general_operand" "")) + (use (match_operand:TF 2 "general_operand" ""))] + "TARGET_HAS_XFLOATING_LIBS" + "alpha_emit_xfloating_arith (PLUS, operands); DONE;") + +(define_insn "*sub3_ieee" + [(set (match_operand:FMODE 0 "register_operand" "=&f") + (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" - "add%,%/ %R1,%R2,%0" + "sub%/ %R1,%R2,%0" [(set_attr "type" "fadd") (set_attr "trap" "yes") (set_attr "round_suffix" "normal") (set_attr "trap_suffix" "u_su_sui")]) -(define_insn "addsf3" - [(set (match_operand:SF 0 "register_operand" "=f") - (plus:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")))] +(define_insn "sub3" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] "TARGET_FP" - "add%,%/ %R1,%R2,%0" + "sub%/ %R1,%R2,%0" [(set_attr "type" "fadd") (set_attr "trap" "yes") (set_attr "round_suffix" "normal") (set_attr "trap_suffix" "u_su_sui")]) -(define_insn "*adddf_ieee" - [(set (match_operand:DF 0 "register_operand" "=&f") - (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" - "add%-%/ %R1,%R2,%0" +(define_insn "*subdf_ext1" + [(set (match_operand:DF 0 "register_operand" "=f") + (minus:DF (float_extend:DF + (match_operand:SF 1 "reg_or_0_operand" "fG")) + (match_operand:DF 2 "reg_or_0_operand" "fG")))] + "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" + "sub%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") (set_attr "trap" "yes") (set_attr "round_suffix" "normal") (set_attr "trap_suffix" "u_su_sui")]) -(define_insn "adddf3" +(define_insn "*subdf_ext2" [(set (match_operand:DF 0 "register_operand" "=f") - (plus:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "add%-%/ %R1,%R2,%0" + (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") + (float_extend:DF + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] + "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" + "sub%-%/ %R1,%R2,%0" [(set_attr "type" "fadd") (set_attr "trap" "yes") (set_attr "round_suffix" "normal") (set_attr "trap_suffix" "u_su_sui")]) -(define_insn "*adddf_ext1" +(define_insn "*subdf_ext3" [(set (match_operand:DF 0 "register_operand" "=f") - (plus:DF (float_extend:DF + (minus:DF (float_extend:DF + (match_operand:SF 1 "reg_or_0_operand" "fG")) + (float_extend:DF + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] + "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" + "sub%-%/ %R1,%R2,%0" + [(set_attr "type" "fadd") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_expand "subtf3" + [(use (match_operand:TF 0 "register_operand" "")) + (use (match_operand:TF 1 "general_operand" "")) + (use (match_operand:TF 2 "general_operand" ""))] + "TARGET_HAS_XFLOATING_LIBS" + "alpha_emit_xfloating_arith (MINUS, operands); DONE;") + +(define_insn "*mul3_ieee" + [(set (match_operand:FMODE 0 "register_operand" "=&f") + (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] + "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" + "mul%/ %R1,%R2,%0" + [(set_attr "type" "fmul") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_insn "mul3" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] + "TARGET_FP" + "mul%/ %R1,%R2,%0" + [(set_attr "type" "fmul") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_insn "*muldf_ext1" + [(set (match_operand:DF 0 "register_operand" "=f") + (mult:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) (match_operand:DF 2 "reg_or_0_operand" "fG")))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "add%-%/ %R1,%R2,%0" - [(set_attr "type" "fadd") + "mul%-%/ %R1,%R2,%0" + [(set_attr "type" "fmul") (set_attr "trap" "yes") (set_attr "round_suffix" "normal") (set_attr "trap_suffix" "u_su_sui")]) -(define_insn "*adddf_ext2" +(define_insn "*muldf_ext2" [(set (match_operand:DF 0 "register_operand" "=f") - (plus:DF (float_extend:DF + (mult:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "%fG")) (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))] "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "add%-%/ %R1,%R2,%0" - [(set_attr "type" "fadd") + "mul%-%/ %R1,%R2,%0" + [(set_attr "type" "fmul") (set_attr "trap" "yes") (set_attr "round_suffix" "normal") (set_attr "trap_suffix" "u_su_sui")]) -(define_expand "addtf3" +(define_expand "multf3" [(use (match_operand:TF 0 "register_operand" "")) (use (match_operand:TF 1 "general_operand" "")) (use (match_operand:TF 2 "general_operand" ""))] "TARGET_HAS_XFLOATING_LIBS" - "alpha_emit_xfloating_arith (PLUS, operands); DONE;") + "alpha_emit_xfloating_arith (MULT, operands); DONE;") +(define_insn "*div3_ieee" + [(set (match_operand:FMODE 0 "register_operand" "=&f") + (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] + "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" + "div%/ %R1,%R2,%0" + [(set_attr "type" "fdiv") + (set_attr "opsize" "") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_insn "div3" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG") + (match_operand:FMODE 2 "reg_or_0_operand" "fG")))] + "TARGET_FP" + "div%/ %R1,%R2,%0" + [(set_attr "type" "fdiv") + (set_attr "opsize" "") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_insn "*divdf_ext1" + [(set (match_operand:DF 0 "register_operand" "=f") + (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) + (match_operand:DF 2 "reg_or_0_operand" "fG")))] + "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" + "div%-%/ %R1,%R2,%0" + [(set_attr "type" "fdiv") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_insn "*divdf_ext2" + [(set (match_operand:DF 0 "register_operand" "=f") + (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") + (float_extend:DF + (match_operand:SF 2 "reg_or_0_operand" "fG"))))] + "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" + "div%-%/ %R1,%R2,%0" + [(set_attr "type" "fdiv") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_insn "*divdf_ext3" + [(set (match_operand:DF 0 "register_operand" "=f") + (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) + (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))] + "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" + "div%-%/ %R1,%R2,%0" + [(set_attr "type" "fdiv") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_expand "divtf3" + [(use (match_operand:TF 0 "register_operand" "")) + (use (match_operand:TF 1 "general_operand" "")) + (use (match_operand:TF 2 "general_operand" ""))] + "TARGET_HAS_XFLOATING_LIBS" + "alpha_emit_xfloating_arith (DIV, operands); DONE;") + +(define_insn "*sqrt2_ieee" + [(set (match_operand:FMODE 0 "register_operand" "=&f") + (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] + "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" + "sqrt%/ %R1,%0" + [(set_attr "type" "fsqrt") + (set_attr "opsize" "") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + +(define_insn "sqrt2" + [(set (match_operand:FMODE 0 "register_operand" "=f") + (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] + "TARGET_FP && TARGET_FIX" + "sqrt%/ %R1,%0" + [(set_attr "type" "fsqrt") + (set_attr "opsize" "") + (set_attr "trap" "yes") + (set_attr "round_suffix" "normal") + (set_attr "trap_suffix" "u_su_sui")]) + ;; Define conversion operators between DFmode and SImode, using the cvtql ;; instruction. To allow combine et al to do useful things, we keep the ;; operation as a unit until after reload, at which point we split the @@ -2270,299 +2423,6 @@ emit_insn (gen_truncdfsf2 (operands[0], tmpf)); DONE; }) - -(define_insn "*divsf3_ieee" - [(set (match_operand:SF 0 "register_operand" "=&f") - (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" - "div%,%/ %R1,%R2,%0" - [(set_attr "type" "fdiv") - (set_attr "opsize" "si") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "divsf3" - [(set (match_operand:SF 0 "register_operand" "=f") - (div:SF (match_operand:SF 1 "reg_or_0_operand" "fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "div%,%/ %R1,%R2,%0" - [(set_attr "type" "fdiv") - (set_attr "opsize" "si") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*divdf3_ieee" - [(set (match_operand:DF 0 "register_operand" "=&f") - (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" - "div%-%/ %R1,%R2,%0" - [(set_attr "type" "fdiv") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "divdf3" - [(set (match_operand:DF 0 "register_operand" "=f") - (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "div%-%/ %R1,%R2,%0" - [(set_attr "type" "fdiv") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*divdf_ext1" - [(set (match_operand:DF 0 "register_operand" "=f") - (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "div%-%/ %R1,%R2,%0" - [(set_attr "type" "fdiv") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*divdf_ext2" - [(set (match_operand:DF 0 "register_operand" "=f") - (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") - (float_extend:DF - (match_operand:SF 2 "reg_or_0_operand" "fG"))))] - "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "div%-%/ %R1,%R2,%0" - [(set_attr "type" "fdiv") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*divdf_ext3" - [(set (match_operand:DF 0 "register_operand" "=f") - (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) - (float_extend:DF (match_operand:SF 2 "reg_or_0_operand" "fG"))))] - "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "div%-%/ %R1,%R2,%0" - [(set_attr "type" "fdiv") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_expand "divtf3" - [(use (match_operand:TF 0 "register_operand" "")) - (use (match_operand:TF 1 "general_operand" "")) - (use (match_operand:TF 2 "general_operand" ""))] - "TARGET_HAS_XFLOATING_LIBS" - "alpha_emit_xfloating_arith (DIV, operands); DONE;") - -(define_insn "*mulsf3_ieee" - [(set (match_operand:SF 0 "register_operand" "=&f") - (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" - "mul%,%/ %R1,%R2,%0" - [(set_attr "type" "fmul") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "mulsf3" - [(set (match_operand:SF 0 "register_operand" "=f") - (mult:SF (match_operand:SF 1 "reg_or_0_operand" "%fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "mul%,%/ %R1,%R2,%0" - [(set_attr "type" "fmul") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*muldf3_ieee" - [(set (match_operand:DF 0 "register_operand" "=&f") - (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" - "mul%-%/ %R1,%R2,%0" - [(set_attr "type" "fmul") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "muldf3" - [(set (match_operand:DF 0 "register_operand" "=f") - (mult:DF (match_operand:DF 1 "reg_or_0_operand" "%fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "mul%-%/ %R1,%R2,%0" - [(set_attr "type" "fmul") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*muldf_ext1" - [(set (match_operand:DF 0 "register_operand" "=f") - (mult:DF (float_extend:DF - (match_operand:SF 1 "reg_or_0_operand" "fG")) - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "mul%-%/ %R1,%R2,%0" - [(set_attr "type" "fmul") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*muldf_ext2" - [(set (match_operand:DF 0 "register_operand" "=f") - (mult:DF (float_extend:DF - (match_operand:SF 1 "reg_or_0_operand" "%fG")) - (float_extend:DF - (match_operand:SF 2 "reg_or_0_operand" "fG"))))] - "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "mul%-%/ %R1,%R2,%0" - [(set_attr "type" "fmul") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_expand "multf3" - [(use (match_operand:TF 0 "register_operand" "")) - (use (match_operand:TF 1 "general_operand" "")) - (use (match_operand:TF 2 "general_operand" ""))] - "TARGET_HAS_XFLOATING_LIBS" - "alpha_emit_xfloating_arith (MULT, operands); DONE;") - -(define_insn "*subsf3_ieee" - [(set (match_operand:SF 0 "register_operand" "=&f") - (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" - "sub%,%/ %R1,%R2,%0" - [(set_attr "type" "fadd") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "subsf3" - [(set (match_operand:SF 0 "register_operand" "=f") - (minus:SF (match_operand:SF 1 "reg_or_0_operand" "fG") - (match_operand:SF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "sub%,%/ %R1,%R2,%0" - [(set_attr "type" "fadd") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*subdf3_ieee" - [(set (match_operand:DF 0 "register_operand" "=&f") - (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" - "sub%-%/ %R1,%R2,%0" - [(set_attr "type" "fadd") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "subdf3" - [(set (match_operand:DF 0 "register_operand" "=f") - (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP" - "sub%-%/ %R1,%R2,%0" - [(set_attr "type" "fadd") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*subdf_ext1" - [(set (match_operand:DF 0 "register_operand" "=f") - (minus:DF (float_extend:DF - (match_operand:SF 1 "reg_or_0_operand" "fG")) - (match_operand:DF 2 "reg_or_0_operand" "fG")))] - "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "sub%-%/ %R1,%R2,%0" - [(set_attr "type" "fadd") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*subdf_ext2" - [(set (match_operand:DF 0 "register_operand" "=f") - (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") - (float_extend:DF - (match_operand:SF 2 "reg_or_0_operand" "fG"))))] - "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "sub%-%/ %R1,%R2,%0" - [(set_attr "type" "fadd") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*subdf_ext3" - [(set (match_operand:DF 0 "register_operand" "=f") - (minus:DF (float_extend:DF - (match_operand:SF 1 "reg_or_0_operand" "fG")) - (float_extend:DF - (match_operand:SF 2 "reg_or_0_operand" "fG"))))] - "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" - "sub%-%/ %R1,%R2,%0" - [(set_attr "type" "fadd") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_expand "subtf3" - [(use (match_operand:TF 0 "register_operand" "")) - (use (match_operand:TF 1 "general_operand" "")) - (use (match_operand:TF 2 "general_operand" ""))] - "TARGET_HAS_XFLOATING_LIBS" - "alpha_emit_xfloating_arith (MINUS, operands); DONE;") - -(define_insn "*sqrtsf2_ieee" - [(set (match_operand:SF 0 "register_operand" "=&f") - (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] - "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" - "sqrt%,%/ %R1,%0" - [(set_attr "type" "fsqrt") - (set_attr "opsize" "si") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "sqrtsf2" - [(set (match_operand:SF 0 "register_operand" "=f") - (sqrt:SF (match_operand:SF 1 "reg_or_0_operand" "fG")))] - "TARGET_FP && TARGET_FIX" - "sqrt%,%/ %R1,%0" - [(set_attr "type" "fsqrt") - (set_attr "opsize" "si") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "*sqrtdf2_ieee" - [(set (match_operand:DF 0 "register_operand" "=&f") - (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] - "TARGET_FP && TARGET_FIX && alpha_fptm >= ALPHA_FPTM_SU" - "sqrt%-%/ %R1,%0" - [(set_attr "type" "fsqrt") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) - -(define_insn "sqrtdf2" - [(set (match_operand:DF 0 "register_operand" "=f") - (sqrt:DF (match_operand:DF 1 "reg_or_0_operand" "fG")))] - "TARGET_FP && TARGET_FIX" - "sqrt%-%/ %R1,%0" - [(set_attr "type" "fsqrt") - (set_attr "trap" "yes") - (set_attr "round_suffix" "normal") - (set_attr "trap_suffix" "u_su_sui")]) ;; Next are all the integer comparisons, and conditional moves and branches ;; and some of the related define_expand's and define_split's. @@ -2979,34 +2839,20 @@ (set_attr "trap" "yes") (set_attr "trap_suffix" "su")]) -(define_insn "*movdfcc_internal" - [(set (match_operand:DF 0 "register_operand" "=f,f") - (if_then_else:DF +(define_insn "*movcc_internal" + [(set (match_operand:FMODE 0 "register_operand" "=f,f") + (if_then_else:FMODE (match_operator 3 "signed_comparison_operator" [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") (match_operand:DF 2 "const0_operand" "G,G")]) - (match_operand:DF 1 "reg_or_0_operand" "fG,0") - (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] + (match_operand:FMODE 1 "reg_or_0_operand" "fG,0") + (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))] "TARGET_FP" "@ fcmov%C3 %R4,%R1,%0 fcmov%D3 %R4,%R5,%0" [(set_attr "type" "fcmov")]) -(define_insn "*movsfcc_internal" - [(set (match_operand:SF 0 "register_operand" "=f,f") - (if_then_else:SF - (match_operator 3 "signed_comparison_operator" - [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") - (match_operand:DF 2 "const0_operand" "G,G")]) - (match_operand:SF 1 "reg_or_0_operand" "fG,0") - (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] - "TARGET_FP" - "@ - fcmov%C3 %R4,%R1,%0 - fcmov%D3 %R4,%R5,%0" - [(set_attr "type" "fcmov")]) - (define_insn "*movdfcc_ext1" [(set (match_operand:DF 0 "register_operand" "=f,f") (if_then_else:DF @@ -3209,27 +3055,18 @@ FAIL; }) -(define_expand "movsfcc" - [(set (match_operand:SF 0 "register_operand" "") - (if_then_else:SF (match_operand 1 "comparison_operator" "") - (match_operand:SF 2 "reg_or_8bit_operand" "") - (match_operand:SF 3 "reg_or_8bit_operand" "")))] +(define_expand "movcc" + [(set (match_operand:FMODE 0 "register_operand" "") + (if_then_else:FMODE + (match_operand 1 "comparison_operator" "") + (match_operand:FMODE 2 "reg_or_8bit_operand" "") + (match_operand:FMODE 3 "reg_or_8bit_operand" "")))] "" { - if ((operands[1] = alpha_emit_conditional_move (operands[1], SFmode)) == 0) + operands[1] = alpha_emit_conditional_move (operands[1], mode); + if (operands[1] == 0) FAIL; }) - -(define_expand "movdfcc" - [(set (match_operand:DF 0 "register_operand" "") - (if_then_else:DF (match_operand 1 "comparison_operator" "") - (match_operand:DF 2 "reg_or_8bit_operand" "") - (match_operand:DF 3 "reg_or_8bit_operand" "")))] - "" -{ - if ((operands[1] = alpha_emit_conditional_move (operands[1], DFmode)) == 0) - FAIL; -}) ;; These define_split definitions are used in cases when comparisons have ;; not be stated in the correct way and we need to reverse the second