diff --git a/arch/arm/include/asm/arch-exynos/clock.h b/arch/arm/include/asm/arch-exynos/clock.h
index fce38ef..1b5c48c 100644
--- a/arch/arm/include/asm/arch-exynos/clock.h
+++ b/arch/arm/include/asm/arch-exynos/clock.h
@@ -251,6 +251,242 @@ struct exynos4_clock {
unsigned int div_iem_l1;
};
+struct exynos4x10_clock {
+ unsigned char res1[0x4200];
+ unsigned int src_leftbus;
+ unsigned char res2[0x1fc];
+ unsigned int mux_stat_leftbus;
+ unsigned char res4[0xfc];
+ unsigned int div_leftbus;
+ unsigned char res5[0xfc];
+ unsigned int div_stat_leftbus;
+ unsigned char res6[0x1fc];
+ unsigned int gate_ip_leftbus;
+ unsigned char res7[0x1fc];
+ unsigned int clkout_leftbus;
+ unsigned int clkout_leftbus_div_stat;
+ unsigned char res8[0x37f8];
+ unsigned int src_rightbus;
+ unsigned char res9[0x1fc];
+ unsigned int mux_stat_rightbus;
+ unsigned char res10[0xfc];
+ unsigned int div_rightbus;
+ unsigned char res11[0xfc];
+ unsigned int div_stat_rightbus;
+ unsigned char res12[0x1fc];
+ unsigned int gate_ip_rightbus;
+ unsigned char res13[0x1fc];
+ unsigned int clkout_rightbus;
+ unsigned int clkout_rightbus_div_stat;
+ unsigned char res14[0x3608];
+ unsigned int epll_lock;
+ unsigned char res15[0xc];
+ unsigned int vpll_lock;
+ unsigned char res16[0xec];
+ unsigned int epll_con0;
+ unsigned int epll_con1;
+ unsigned char res17[0x8];
+ unsigned int vpll_con0;
+ unsigned int vpll_con1;
+ unsigned char res18[0xe8];
+ unsigned int src_top0;
+ unsigned int src_top1;
+ unsigned char res19[0x8];
+ unsigned int src_cam;
+ unsigned int src_tv;
+ unsigned int src_mfc;
+ unsigned int src_g3d;
+ unsigned int src_image;
+ unsigned int src_lcd0;
+ unsigned int src_lcd1;
+ unsigned int src_maudio;
+ unsigned int src_fsys;
+ unsigned char res20[0xc];
+ unsigned int src_peril0;
+ unsigned int src_peril1;
+ unsigned char res21[0xb8];
+ unsigned int src_mask_top;
+ unsigned char res22[0xc];
+ unsigned int src_mask_cam;
+ unsigned int src_mask_tv;
+ unsigned char res23[0xc];
+ unsigned int src_mask_lcd0;
+ unsigned int src_mask_lcd1;
+ unsigned int src_mask_maudio;
+ unsigned int src_mask_fsys;
+ unsigned char res24[0xc];
+ unsigned int src_mask_peril0;
+ unsigned int src_mask_peril1;
+ unsigned char res25[0xb8];
+ unsigned int mux_stat_top;
+ unsigned char res26[0x14];
+ unsigned int mux_stat_mfc;
+ unsigned int mux_stat_g3d;
+ unsigned int mux_stat_image;
+ unsigned char res27[0xdc];
+ unsigned int div_top;
+ unsigned char res28[0xc];
+ unsigned int div_cam;
+ unsigned int div_tv;
+ unsigned int div_mfc;
+ unsigned int div_g3d;
+ unsigned int div_image;
+ unsigned int div_lcd0;
+ unsigned int div_lcd1;
+ unsigned int div_maudio;
+ unsigned int div_fsys0;
+ unsigned int div_fsys1;
+ unsigned int div_fsys2;
+ unsigned int div_fsys3;
+ unsigned int div_peril0;
+ unsigned int div_peril1;
+ unsigned int div_peril2;
+ unsigned int div_peril3;
+ unsigned int div_peril4;
+ unsigned int div_peril5;
+ unsigned char res29[0x18];
+ unsigned int div2_ratio;
+ unsigned char res30[0x8c];
+ unsigned int div_stat_top;
+ unsigned char res31[0xc];
+ unsigned int div_stat_cam;
+ unsigned int div_stat_tv;
+ unsigned int div_stat_mfc;
+ unsigned int div_stat_g3d;
+ unsigned int div_stat_image;
+ unsigned int div_stat_lcd0;
+ unsigned int div_stat_lcd1;
+ unsigned int div_stat_maudio;
+ unsigned int div_stat_fsys0;
+ unsigned int div_stat_fsys1;
+ unsigned int div_stat_fsys2;
+ unsigned int div_stat_fsys3;
+ unsigned int div_stat_peril0;
+ unsigned int div_stat_peril1;
+ unsigned int div_stat_peril2;
+ unsigned int div_stat_peril3;
+ unsigned int div_stat_peril4;
+ unsigned int div_stat_peril5;
+ unsigned char res32[0x18];
+ unsigned int div2_stat;
+ unsigned char res33[0x19c];
+ unsigned int gate_sclk_cam;
+ unsigned char res34[0x0fc];
+ unsigned int gate_ip_cam;
+ unsigned int gate_ip_tv;
+ unsigned int gate_ip_mfc;
+ unsigned int gate_ip_g3d;
+ unsigned int gate_ip_image;
+ unsigned int gate_ip_lcd0;
+ unsigned int gate_ip_lcd1;
+ unsigned char res35[0x4];
+ unsigned int gate_ip_fsys;
+ unsigned char res36[0x8];
+ unsigned int gate_ip_gps;
+ unsigned int gate_ip_peril;
+ unsigned char res37[0xc];
+ unsigned int gate_ip_perir;
+ unsigned char res38[0xc];
+ unsigned int gate_block;
+ unsigned char res39[0x8c];
+ unsigned int clkout_cmu_top;
+ unsigned int clkout_cmu_top_div_stat;
+ unsigned char res40[0x37f8];
+ unsigned int src_dmc;
+ unsigned char res41[0xfc];
+ unsigned int src_mask_dmc;
+ unsigned char res42[0xfc];
+ unsigned int mux_stat_dmc;
+ unsigned char res43[0xfc];
+ unsigned int div_dmc0;
+ unsigned int div_dmc1;
+ unsigned char res44[0xf8];
+ unsigned int div_stat_dmc0;
+ unsigned int div_stat_dmc1;
+ unsigned char res45[0x2f8];
+ unsigned int gate_ip_dmc;
+ unsigned char res46[0xfc];
+ unsigned int clkout_cmu_dmc;
+ unsigned int clkout_cmu_dmc_div_stat;
+ unsigned char res47[0x5f8];
+ unsigned int dcgidx_map0;
+ unsigned int dcgidx_map1;
+ unsigned int dcgidx_map2;
+ unsigned char res48[0x14];
+ unsigned int dcgperf_map0;
+ unsigned int dcgperf_map1;
+ unsigned char res49[0x18];
+ unsigned int dvcidx_map;
+ unsigned char res50[0x1c];
+ unsigned int freq_cpu;
+ unsigned int freq_dpm;
+ unsigned char res51[0x18];
+ unsigned int dvsemclk_en;
+ unsigned int maxperf;
+ unsigned char res52[0x2f78];
+ unsigned int apll_lock;
+ unsigned char res53[0x4];
+ unsigned int mpll_lock;
+ unsigned char res54[0xf4];
+ unsigned int apll_con0;
+ unsigned int apll_con1;
+ unsigned int mpll_con0;
+ unsigned int mpll_con1;
+ unsigned char res55[0xf0];
+ unsigned int src_cpu;
+ unsigned char res56[0x1fc];
+ unsigned int mux_stat_cpu;
+ unsigned char res57[0xfc];
+ unsigned int div_cpu0;
+ unsigned int div_cpu1;
+ unsigned char res58[0xf8];
+ unsigned int div_stat_cpu0;
+ unsigned int div_stat_cpu1;
+ unsigned char res59[0x1f8];
+ unsigned int gate_sclk_cpu;
+ unsigned char res60[0x0fc];
+ unsigned int gate_ip_cpu;
+ unsigned char res61[0x0fc];
+ unsigned int clkout_cmu_cpu;
+ unsigned int clkout_cmu_cpu_div_stat;
+ unsigned char res62[0x5f8];
+ unsigned int armclk_stopctrl;
+ unsigned int atclk_stopctrl;
+ unsigned char res63[0x8];
+ unsigned int parityfail_status;
+ unsigned int parityfail_clear;
+ unsigned char res64[0x8];
+ unsigned int pwr_ctrl;
+ unsigned char res65[0xdc];
+ unsigned int apll_con0_l8;
+ unsigned int apll_con0_l7;
+ unsigned int apll_con0_l6;
+ unsigned int apll_con0_l5;
+ unsigned int apll_con0_l4;
+ unsigned int apll_con0_l3;
+ unsigned int apll_con0_l2;
+ unsigned int apll_con0_l1;
+ unsigned int iem_control;
+ unsigned char res66[0xdc];
+ unsigned int apll_con1_l8;
+ unsigned int apll_con1_l7;
+ unsigned int apll_con1_l6;
+ unsigned int apll_con1_l5;
+ unsigned int apll_con1_l4;
+ unsigned int apll_con1_l3;
+ unsigned int apll_con1_l2;
+ unsigned int apll_con1_l1;
+ unsigned char res67[0xe0];
+ unsigned int div_iem_l8;
+ unsigned int div_iem_l7;
+ unsigned int div_iem_l6;
+ unsigned int div_iem_l5;
+ unsigned int div_iem_l4;
+ unsigned int div_iem_l3;
+ unsigned int div_iem_l2;
+ unsigned int div_iem_l1;
+};
+
struct exynos5_clock {
unsigned int apll_lock;
unsigned char res1[0xfc];