From patchwork Fri Oct 12 12:36:15 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Riku Voipio X-Patchwork-Id: 191123 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 73C442C008B for ; Sat, 13 Oct 2012 00:02:03 +1100 (EST) Received: from localhost ([::1]:56142 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMeUB-00018f-2P for incoming@patchwork.ozlabs.org; Fri, 12 Oct 2012 08:37:03 -0400 Received: from eggs.gnu.org ([208.118.235.92]:43663) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMeTV-0007iG-LL for qemu-devel@nongnu.org; Fri, 12 Oct 2012 08:36:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TMeTT-0004og-DV for qemu-devel@nongnu.org; Fri, 12 Oct 2012 08:36:21 -0400 Received: from afflict.kos.to ([92.243.29.197]:49352) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TMeTT-0004nd-6X for qemu-devel@nongnu.org; Fri, 12 Oct 2012 08:36:19 -0400 Received: by afflict.kos.to (Postfix, from userid 1000) id 90321264CE; Fri, 12 Oct 2012 14:36:16 +0200 (CEST) From: riku.voipio@linaro.org To: qemu-devel@nongnu.org Date: Fri, 12 Oct 2012 15:36:15 +0300 Message-Id: <4a1def4e4ec2f0eb72b15596a04a030cdc889370.1350044677.git.riku.voipio@linaro.org> X-Mailer: git-send-email 1.7.2.5 In-Reply-To: References: X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 92.243.29.197 Cc: Alexander Graf Subject: [Qemu-devel] [PATCH 10/11] linux-user: ppc: mark as long long aligned X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Alexander Graf The SysV PPC32 ABI dictates that long long (64bit) parameters are pass in odd/even register pairs. Because unlike ARM and MIPS we start at an odd register number, we can reuse the same aligning code that ARM and MIPS use. Clarified inline comment that it is SysV ABI that requires long long aligned parameters - Riku Signed-off-by: Alexander Graf Signed-off-by: Riku Voipio --- linux-user/syscall.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 009bf8f..3da8e51 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -587,12 +587,17 @@ extern int setfsgid(int); extern int setgroups(int, gid_t *); /* ARM EABI and MIPS expect 64bit types aligned even on pairs or registers */ -#ifdef TARGET_ARM +#ifdef TARGET_ARM static inline int regpairs_aligned(void *cpu_env) { return ((((CPUARMState *)cpu_env)->eabi) == 1) ; } #elif defined(TARGET_MIPS) static inline int regpairs_aligned(void *cpu_env) { return 1; } +#elif defined(TARGET_PPC) && !defined(TARGET_PPC64) +/* SysV AVI for PPC32 expects 64bit parameters to be passed on odd/even pairs + * of registers which translates to the same as ARM/MIPS, because we start with + * r3 as arg1 */ +static inline int regpairs_aligned(void *cpu_env) { return 1; } #else static inline int regpairs_aligned(void *cpu_env) { return 0; } #endif