Patchwork [1/9] cadence_ttc: Fix 'clear on read' behavior

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Submitter Peter Maydell
Date Oct. 12, 2012, 11:38 a.m.
Message ID <1350041912-12595-2-git-send-email-peter.maydell@linaro.org>
Download mbox | patch
Permalink /patch/191110/
State New
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Comments

Peter Maydell - Oct. 12, 2012, 11:38 a.m.
From: Soren Brinkmann <soren.brinkmann@xilinx.com>

A missing call to qemu_set_irq() when reading the IRQ register
required SW to write to the IRQ register to acknowledge an
interrupt. With this patch the behavior is fixed:
 - Reading the interrupt register clears it and updates the timers
   interrupt status
 - Writes to the interrupt register are ignored

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/cadence_ttc.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/hw/cadence_ttc.c b/hw/cadence_ttc.c
index dd02f86..77b6976 100644
--- a/hw/cadence_ttc.c
+++ b/hw/cadence_ttc.c
@@ -274,6 +274,7 @@  static uint32_t cadence_ttc_read_imp(void *opaque, target_phys_addr_t offset)
         /* cleared after read */
         value = s->reg_intr;
         s->reg_intr = 0;
+        cadence_timer_update(s);
         return value;
 
     case 0x60: /* interrupt enable */
@@ -355,7 +356,6 @@  static void cadence_ttc_write(void *opaque, target_phys_addr_t offset,
     case 0x54: /* interrupt register */
     case 0x58:
     case 0x5c:
-        s->reg_intr &= (~value & 0xfff);
         break;
 
     case 0x60: /* interrupt enable */