Patchwork [qom-cpu,v2,2/7] apic: Store X86CPU in APICCommonState

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Submitter Andreas Färber
Date Oct. 12, 2012, 1:26 a.m.
Message ID <1350005203-15405-3-git-send-email-afaerber@suse.de>
Download mbox | patch
Permalink /patch/191039/
State New
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Comments

Andreas Färber - Oct. 12, 2012, 1:26 a.m.
Prepares for using a link<> property to connect APIC with CPU and for
changing the CPU APIs to CPUState.

Resolve Coding Style warnings by moving the closing parenthesis of
foreach_apic() macro to next line.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Cc: Igor Mammedov <imammedo@redhat.com>
---
 hw/apic.c          |   38 +++++++++++++++++++++-----------------
 hw/apic_common.c   |    4 ++--
 hw/apic_internal.h |    3 ++-
 hw/kvm/apic.c      |    8 ++++----
 target-i386/cpu.c  |    2 +-
 5 Dateien geändert, 30 Zeilen hinzugefügt(+), 25 Zeilen entfernt(-)
Igor Mammedov - Oct. 15, 2012, 11:28 p.m.
On Fri, 12 Oct 2012 03:26:38 +0200
Andreas Färber <afaerber@suse.de> wrote:

> Prepares for using a link<> property to connect APIC with CPU and for
> changing the CPU APIs to CPUState.
> 
> Resolve Coding Style warnings by moving the closing parenthesis of
> foreach_apic() macro to next line.
> 
> Signed-off-by: Andreas Färber <afaerber@suse.de>
> Cc: Igor Mammedov <imammedo@redhat.com>
> ---
>  hw/apic.c          |   38 +++++++++++++++++++++-----------------
>  hw/apic_common.c   |    4 ++--
>  hw/apic_internal.h |    3 ++-
>  hw/kvm/apic.c      |    8 ++++----
>  target-i386/cpu.c  |    2 +-
>  5 Dateien geändert, 30 Zeilen hinzugefügt(+), 25 Zeilen entfernt(-)
> 
> diff --git a/hw/apic.c b/hw/apic.c
> index 385555e..f1f804d 100644
> --- a/hw/apic.c
> +++ b/hw/apic.c
> @@ -107,7 +107,7 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type)
>          length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
>  
>          if (sync_type & SYNC_TO_VAPIC) {
> -            assert(qemu_cpu_is_self(s->cpu_env));
> +            assert(qemu_cpu_is_self(&s->cpu->env));
>  
>              vapic_state.tpr = s->tpr;
>              vapic_state.enabled = 1;
> @@ -151,15 +151,15 @@ static void apic_local_deliver(APICCommonState *s, int vector)
>  
>      switch ((lvt >> 8) & 7) {
>      case APIC_DM_SMI:
> -        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
> +        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI);
>          break;
>  
>      case APIC_DM_NMI:
> -        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
> +        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI);
>          break;
>  
>      case APIC_DM_EXTINT:
> -        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
> +        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
>          break;
>  
>      case APIC_DM_FIXED:
> @@ -187,7 +187,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level)
>              reset_bit(s->irr, lvt & 0xff);
>              /* fall through */
>          case APIC_DM_EXTINT:
> -            cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
> +            cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
>              break;
>          }
>      }
> @@ -248,18 +248,22 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask,
>  
>          case APIC_DM_SMI:
>              foreach_apic(apic_iter, deliver_bitmask,
> -                cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
> +                cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI)
> +            );
>              return;
>  
>          case APIC_DM_NMI:
>              foreach_apic(apic_iter, deliver_bitmask,
> -                cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
> +                cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI)
> +            );
>              return;
>  
>          case APIC_DM_INIT:
>              /* normal INIT IPI sent to processors */
>              foreach_apic(apic_iter, deliver_bitmask,
> -                         cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
> +                         cpu_interrupt(&apic_iter->cpu->env,
> +                                       CPU_INTERRUPT_INIT)
> +            );
>              return;
>  
>          case APIC_DM_EXTINT:
> @@ -293,7 +297,7 @@ static void apic_set_base(APICCommonState *s, uint64_t val)
>      /* if disabled, cannot be enabled again */
>      if (!(val & MSR_IA32_APICBASE_ENABLE)) {
>          s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
> -        cpu_clear_apic_feature(s->cpu_env);
> +        cpu_clear_apic_feature(&s->cpu->env);
>          s->spurious_vec &= ~APIC_SV_ENABLE;
>      }
>  }
> @@ -362,10 +366,10 @@ static void apic_update_irq(APICCommonState *s)
>      if (!(s->spurious_vec & APIC_SV_ENABLE)) {
>          return;
>      }
> -    if (!qemu_cpu_is_self(s->cpu_env)) {
> -        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_POLL);
> +    if (!qemu_cpu_is_self(&s->cpu->env)) {
> +        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL);
>      } else if (apic_irq_pending(s) > 0) {
> -        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
> +        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
>      }
>  }
>  
> @@ -472,18 +476,18 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
>  static void apic_startup(APICCommonState *s, int vector_num)
>  {
>      s->sipi_vector = vector_num;
> -    cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
> +    cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
>  }
>  
>  void apic_sipi(DeviceState *d)
>  {
>      APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
>  
> -    cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
> +    cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
>  
>      if (!s->wait_for_sipi)
>          return;
> -    cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
> +    cpu_x86_load_seg_cache_sipi(&s->cpu->env, s->sipi_vector);
>      s->wait_for_sipi = 0;
>  }
>  
> @@ -672,7 +676,7 @@ static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
>      case 0x08:
>          apic_sync_vapic(s, SYNC_FROM_VAPIC);
>          if (apic_report_tpr_access) {
> -            cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ);
> +            cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
>          }
>          val = s->tpr;
>          break;
> @@ -774,7 +778,7 @@ static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
>          break;
>      case 0x08:
>          if (apic_report_tpr_access) {
> -            cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE);
> +            cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
>          }
>          s->tpr = val;
>          apic_sync_vapic(s, SYNC_TO_VAPIC);
> diff --git a/hw/apic_common.c b/hw/apic_common.c
> index a26a631..7e5af39 100644
> --- a/hw/apic_common.c
> +++ b/hw/apic_common.c
> @@ -103,7 +103,7 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
>  {
>      APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
>  
> -    vapic_report_tpr_access(s->vapic, s->cpu_env, ip, access);
> +    vapic_report_tpr_access(s->vapic, &s->cpu->env, ip, access);
>  }
>  
>  void apic_report_irq_delivered(int delivered)
> @@ -217,7 +217,7 @@ static void apic_reset_common(DeviceState *d)
>      APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
>      bool bsp;
>  
> -    bsp = cpu_is_bsp(x86_env_get_cpu(s->cpu_env));
> +    bsp = cpu_is_bsp(s->cpu);
>      s->apicbase = 0xfee00000 |
>          (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
>  
> diff --git a/hw/apic_internal.h b/hw/apic_internal.h
> index 4d8ff49..983671b 100644
> --- a/hw/apic_internal.h
> +++ b/hw/apic_internal.h
> @@ -95,8 +95,9 @@ typedef struct APICCommonClass
>  
>  struct APICCommonState {
>      SysBusDevice busdev;
> +
>      MemoryRegion io_memory;
> -    void *cpu_env;
> +    X86CPU *cpu;
>      uint32_t apicbase;
>      uint8_t id;
>      uint8_t arb_id;
> diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c
> index 80e3e48..fddb5ca 100644
> --- a/hw/kvm/apic.c
> +++ b/hw/kvm/apic.c
> @@ -104,7 +104,7 @@ static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable)
>          .enabled = enable
>      };
>  
> -    kvm_vcpu_ioctl(s->cpu_env, KVM_TPR_ACCESS_REPORTING, &ctl);
> +    kvm_vcpu_ioctl(&s->cpu->env, KVM_TPR_ACCESS_REPORTING, &ctl);
>  }
>  
>  static void kvm_apic_vapic_base_update(APICCommonState *s)
> @@ -114,7 +114,7 @@ static void kvm_apic_vapic_base_update(APICCommonState *s)
>      };
>      int ret;
>  
> -    ret = kvm_vcpu_ioctl(s->cpu_env, KVM_SET_VAPIC_ADDR, &vapid_addr);
> +    ret = kvm_vcpu_ioctl(&s->cpu->env, KVM_SET_VAPIC_ADDR, &vapid_addr);
>      if (ret < 0) {
>          fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n",
>                  strerror(-ret));
> @@ -125,7 +125,7 @@ static void kvm_apic_vapic_base_update(APICCommonState *s)
>  static void do_inject_external_nmi(void *data)
>  {
>      APICCommonState *s = data;
> -    CPUX86State *env = s->cpu_env;
> +    CPUX86State *env = &s->cpu->env;
>      uint32_t lvt;
>      int ret;
>  
> @@ -143,7 +143,7 @@ static void do_inject_external_nmi(void *data)
>  
>  static void kvm_apic_external_nmi(APICCommonState *s)
>  {
> -    run_on_cpu(s->cpu_env, do_inject_external_nmi, s);
> +    run_on_cpu(&s->cpu->env, do_inject_external_nmi, s);
>  }
>  
>  static uint64_t kvm_apic_mem_read(void *opaque, target_phys_addr_t addr,
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> index 0cce910..6a9cacf 100644
> --- a/target-i386/cpu.c
> +++ b/target-i386/cpu.c
> @@ -1905,7 +1905,7 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
>      qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
>      /* TODO: convert to link<> */
>      apic = APIC_COMMON(env->apic_state);
> -    apic->cpu_env = env;
> +    apic->cpu = cpu;
>  
>      if (qdev_init(env->apic_state)) {
>          error_setg(errp, "APIC device '%s' could not be initialized",
> -- 
> 1.7.10.4
> 
> 
Reviewed-by: Igor Mammedov <imammedo@redhat.com>

Patch

diff --git a/hw/apic.c b/hw/apic.c
index 385555e..f1f804d 100644
--- a/hw/apic.c
+++ b/hw/apic.c
@@ -107,7 +107,7 @@  static void apic_sync_vapic(APICCommonState *s, int sync_type)
         length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr);
 
         if (sync_type & SYNC_TO_VAPIC) {
-            assert(qemu_cpu_is_self(s->cpu_env));
+            assert(qemu_cpu_is_self(&s->cpu->env));
 
             vapic_state.tpr = s->tpr;
             vapic_state.enabled = 1;
@@ -151,15 +151,15 @@  static void apic_local_deliver(APICCommonState *s, int vector)
 
     switch ((lvt >> 8) & 7) {
     case APIC_DM_SMI:
-        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
+        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI);
         break;
 
     case APIC_DM_NMI:
-        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
+        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI);
         break;
 
     case APIC_DM_EXTINT:
-        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
+        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
         break;
 
     case APIC_DM_FIXED:
@@ -187,7 +187,7 @@  void apic_deliver_pic_intr(DeviceState *d, int level)
             reset_bit(s->irr, lvt & 0xff);
             /* fall through */
         case APIC_DM_EXTINT:
-            cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
+            cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
             break;
         }
     }
@@ -248,18 +248,22 @@  static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 
         case APIC_DM_SMI:
             foreach_apic(apic_iter, deliver_bitmask,
-                cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
+                cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI)
+            );
             return;
 
         case APIC_DM_NMI:
             foreach_apic(apic_iter, deliver_bitmask,
-                cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
+                cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI)
+            );
             return;
 
         case APIC_DM_INIT:
             /* normal INIT IPI sent to processors */
             foreach_apic(apic_iter, deliver_bitmask,
-                         cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
+                         cpu_interrupt(&apic_iter->cpu->env,
+                                       CPU_INTERRUPT_INIT)
+            );
             return;
 
         case APIC_DM_EXTINT:
@@ -293,7 +297,7 @@  static void apic_set_base(APICCommonState *s, uint64_t val)
     /* if disabled, cannot be enabled again */
     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
-        cpu_clear_apic_feature(s->cpu_env);
+        cpu_clear_apic_feature(&s->cpu->env);
         s->spurious_vec &= ~APIC_SV_ENABLE;
     }
 }
@@ -362,10 +366,10 @@  static void apic_update_irq(APICCommonState *s)
     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
         return;
     }
-    if (!qemu_cpu_is_self(s->cpu_env)) {
-        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_POLL);
+    if (!qemu_cpu_is_self(&s->cpu->env)) {
+        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL);
     } else if (apic_irq_pending(s) > 0) {
-        cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
+        cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD);
     }
 }
 
@@ -472,18 +476,18 @@  static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 static void apic_startup(APICCommonState *s, int vector_num)
 {
     s->sipi_vector = vector_num;
-    cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
+    cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
 }
 
 void apic_sipi(DeviceState *d)
 {
     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 
-    cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
+    cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI);
 
     if (!s->wait_for_sipi)
         return;
-    cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
+    cpu_x86_load_seg_cache_sipi(&s->cpu->env, s->sipi_vector);
     s->wait_for_sipi = 0;
 }
 
@@ -672,7 +676,7 @@  static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
     case 0x08:
         apic_sync_vapic(s, SYNC_FROM_VAPIC);
         if (apic_report_tpr_access) {
-            cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ);
+            cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ);
         }
         val = s->tpr;
         break;
@@ -774,7 +778,7 @@  static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
         break;
     case 0x08:
         if (apic_report_tpr_access) {
-            cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE);
+            cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE);
         }
         s->tpr = val;
         apic_sync_vapic(s, SYNC_TO_VAPIC);
diff --git a/hw/apic_common.c b/hw/apic_common.c
index a26a631..7e5af39 100644
--- a/hw/apic_common.c
+++ b/hw/apic_common.c
@@ -103,7 +103,7 @@  void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
 {
     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 
-    vapic_report_tpr_access(s->vapic, s->cpu_env, ip, access);
+    vapic_report_tpr_access(s->vapic, &s->cpu->env, ip, access);
 }
 
 void apic_report_irq_delivered(int delivered)
@@ -217,7 +217,7 @@  static void apic_reset_common(DeviceState *d)
     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
     bool bsp;
 
-    bsp = cpu_is_bsp(x86_env_get_cpu(s->cpu_env));
+    bsp = cpu_is_bsp(s->cpu);
     s->apicbase = 0xfee00000 |
         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
 
diff --git a/hw/apic_internal.h b/hw/apic_internal.h
index 4d8ff49..983671b 100644
--- a/hw/apic_internal.h
+++ b/hw/apic_internal.h
@@ -95,8 +95,9 @@  typedef struct APICCommonClass
 
 struct APICCommonState {
     SysBusDevice busdev;
+
     MemoryRegion io_memory;
-    void *cpu_env;
+    X86CPU *cpu;
     uint32_t apicbase;
     uint8_t id;
     uint8_t arb_id;
diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c
index 80e3e48..fddb5ca 100644
--- a/hw/kvm/apic.c
+++ b/hw/kvm/apic.c
@@ -104,7 +104,7 @@  static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable)
         .enabled = enable
     };
 
-    kvm_vcpu_ioctl(s->cpu_env, KVM_TPR_ACCESS_REPORTING, &ctl);
+    kvm_vcpu_ioctl(&s->cpu->env, KVM_TPR_ACCESS_REPORTING, &ctl);
 }
 
 static void kvm_apic_vapic_base_update(APICCommonState *s)
@@ -114,7 +114,7 @@  static void kvm_apic_vapic_base_update(APICCommonState *s)
     };
     int ret;
 
-    ret = kvm_vcpu_ioctl(s->cpu_env, KVM_SET_VAPIC_ADDR, &vapid_addr);
+    ret = kvm_vcpu_ioctl(&s->cpu->env, KVM_SET_VAPIC_ADDR, &vapid_addr);
     if (ret < 0) {
         fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n",
                 strerror(-ret));
@@ -125,7 +125,7 @@  static void kvm_apic_vapic_base_update(APICCommonState *s)
 static void do_inject_external_nmi(void *data)
 {
     APICCommonState *s = data;
-    CPUX86State *env = s->cpu_env;
+    CPUX86State *env = &s->cpu->env;
     uint32_t lvt;
     int ret;
 
@@ -143,7 +143,7 @@  static void do_inject_external_nmi(void *data)
 
 static void kvm_apic_external_nmi(APICCommonState *s)
 {
-    run_on_cpu(s->cpu_env, do_inject_external_nmi, s);
+    run_on_cpu(&s->cpu->env, do_inject_external_nmi, s);
 }
 
 static uint64_t kvm_apic_mem_read(void *opaque, target_phys_addr_t addr,
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 0cce910..6a9cacf 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1905,7 +1905,7 @@  static void x86_cpu_apic_init(X86CPU *cpu, Error **errp)
     qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id);
     /* TODO: convert to link<> */
     apic = APIC_COMMON(env->apic_state);
-    apic->cpu_env = env;
+    apic->cpu = cpu;
 
     if (qdev_init(env->apic_state)) {
         error_setg(errp, "APIC device '%s' could not be initialized",