Patchwork [U-Boot,4/4] powerpc/b4860qds: Add B4860QDS board

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Submitter York Sun
Date Oct. 11, 2012, 5:13 p.m.
Message ID <1349975620-21163-4-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/190968/
State Superseded
Delegated to: Andy Fleming
Headers show

Comments

York Sun - Oct. 11, 2012, 5:13 p.m.
B4860QDS is a high-performance computing evaluation, development and
test platform supporting the B4860 QorIQ Power Architectureâ„¢ processor.

VSC3316 is 11.5Gbps 16x16 Asynchronous cross-point switch and
VSC3308 is 11.5Gbps 8x8 Asynchronous cross-point switch,
these crosspoint switches commute SerDes lanes to different destinations
depending upon their programming in accordance with SerDes protocol

1) Add defines for VSC3316/3308 crosspoint switches
2) Add define for PCA-I2C bus multiplexer
3) Add support in b4860qds board file to configure these
   crosspoint switches based on the SerDes1 and SerDes2 protocol
4) Add VSC3316 and VSC3308 Mux entries for all possible crosspoint
   connections on b4860qds board

B4860 has FMANv3 so the External PHYs are accessible using dedicated MDIO blocks
at addresse 0x4fc0000 0x4fd0000.
B4860 has only SGMII, no RGMII, single FMAN.

 Slot and PHYs details on B4860QDS
 -----------------------------------
        - Two on board SGMII PHYs connected through serdes1 via crossbar
        - Two slots available via AMC2PEX connector through serdes2
        - Slot1 (PCIe/ SGMII riser/ XAUI)
          connected to serdes2 lanes 0,1,2,3
        - Slot2 (PCIe/ SGMII Riser/ XAUI)
          connected to serdes2 lanes 4,5,6,7 via crossbar

Cross bar is a Vitesse switch on B4860 QDS which is connected to serdes
on one side(input) and the PHYs(output) on the other side.
So this device needs to be configured to get the right serdes lanes go to the
right PHYs and slots. Cross bar configurations done based on the RCW.

Currently the below mentioned are tested and supported:
        1. sgmii5 and sgmii6 are connected to onboard PHYs
        srds1_prtcl=0x2A
        2. sgmii 1, sgmiii2, sgmii3, sgmii4 via SGMII riser card on Slot#1
        srds2_prtcl=0x18

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
---
 board/freescale/b4860qds/Makefile                |   54 ++
 board/freescale/b4860qds/b4860qds.c              |  444 ++++++++++++
 board/freescale/b4860qds/b4860qds.h              |   26 +
 board/freescale/b4860qds/b4860qds_crossbar_con.h |   58 ++
 board/freescale/b4860qds/b4860qds_qixis.h        |   47 ++
 board/freescale/b4860qds/ddr.c                   |  190 +++++
 board/freescale/b4860qds/eth_b4860qds.c          |  287 ++++++++
 board/freescale/b4860qds/law.c                   |   44 ++
 board/freescale/b4860qds/pci.c                   |   39 ++
 board/freescale/b4860qds/tlb.c                   |  122 ++++
 boards.cfg                                       |    2 +
 doc/README.b4860qds                              |   20 +
 include/configs/B4860QDS.h                       |  812 ++++++++++++++++++++++
 13 files changed, 2145 insertions(+)
 create mode 100644 board/freescale/b4860qds/Makefile
 create mode 100644 board/freescale/b4860qds/b4860qds.c
 create mode 100644 board/freescale/b4860qds/b4860qds.h
 create mode 100644 board/freescale/b4860qds/b4860qds_crossbar_con.h
 create mode 100644 board/freescale/b4860qds/b4860qds_qixis.h
 create mode 100644 board/freescale/b4860qds/ddr.c
 create mode 100644 board/freescale/b4860qds/eth_b4860qds.c
 create mode 100644 board/freescale/b4860qds/law.c
 create mode 100644 board/freescale/b4860qds/pci.c
 create mode 100644 board/freescale/b4860qds/tlb.c
 create mode 100644 doc/README.b4860qds
 create mode 100644 include/configs/B4860QDS.h
Andy Fleming - Oct. 22, 2012, 8:55 p.m.
On Thu, Oct 11, 2012 at 12:13 PM, York Sun <yorksun@freescale.com> wrote:
> B4860QDS is a high-performance computing evaluation, development and
> test platform supporting the B4860 QorIQ Power Architectureâ„¢ processor.
>
> VSC3316 is 11.5Gbps 16x16 Asynchronous cross-point switch and
> VSC3308 is 11.5Gbps 8x8 Asynchronous cross-point switch,
> these crosspoint switches commute SerDes lanes to different destinations
> depending upon their programming in accordance with SerDes protocol
>
> 1) Add defines for VSC3316/3308 crosspoint switches
> 2) Add define for PCA-I2C bus multiplexer
> 3) Add support in b4860qds board file to configure these
>    crosspoint switches based on the SerDes1 and SerDes2 protocol
> 4) Add VSC3316 and VSC3308 Mux entries for all possible crosspoint
>    connections on b4860qds board
>
> B4860 has FMANv3 so the External PHYs are accessible using dedicated MDIO blocks
> at addresse 0x4fc0000 0x4fd0000.
> B4860 has only SGMII, no RGMII, single FMAN.
>
>  Slot and PHYs details on B4860QDS
>  -----------------------------------
>         - Two on board SGMII PHYs connected through serdes1 via crossbar
>         - Two slots available via AMC2PEX connector through serdes2
>         - Slot1 (PCIe/ SGMII riser/ XAUI)
>           connected to serdes2 lanes 0,1,2,3
>         - Slot2 (PCIe/ SGMII Riser/ XAUI)
>           connected to serdes2 lanes 4,5,6,7 via crossbar
>
> Cross bar is a Vitesse switch on B4860 QDS which is connected to serdes
> on one side(input) and the PHYs(output) on the other side.
> So this device needs to be configured to get the right serdes lanes go to the
> right PHYs and slots. Cross bar configurations done based on the RCW.
>
> Currently the below mentioned are tested and supported:
>         1. sgmii5 and sgmii6 are connected to onboard PHYs
>         srds1_prtcl=0x2A
>         2. sgmii 1, sgmiii2, sgmii3, sgmii4 via SGMII riser card on Slot#1
>         srds2_prtcl=0x18
>
> Signed-off-by: York Sun <yorksun@freescale.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
> Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
> Signed-off-by: Sandeep Singh <Sandeep@freescale.com>
> ---


Please note that, due to compile issues brought on by not defining
QIXIS_RST_CTL_RESET and other similar constants, the B4860QDS code
cannot be applied to the tree. Internal review indicates that these
features are implemented differently on B4QDS, and the code needs to
be updated to reflect that.

Andy

Patch

diff --git a/board/freescale/b4860qds/Makefile b/board/freescale/b4860qds/Makefile
new file mode 100644
index 0000000..06018f4
--- /dev/null
+++ b/board/freescale/b4860qds/Makefile
@@ -0,0 +1,54 @@ 
+#
+# Copyright 2012 Freescale Semiconductor, Inc.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS-y	+= $(BOARD).o
+COBJS-y	+= ddr.o
+COBJS-$(CONFIG_B4860QDS)+= eth_b4860qds.o
+COBJS-$(CONFIG_PCI)	+= pci.o
+COBJS-y	+= law.o
+COBJS-y	+= tlb.o
+
+SRCS	:= $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(call cmd_link_o_target, $(OBJS))
+
+clean:
+	rm -f $(OBJS) $(SOBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/freescale/b4860qds/b4860qds.c b/board/freescale/b4860qds/b4860qds.c
new file mode 100644
index 0000000..91e0d34
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds.c
@@ -0,0 +1,444 @@ 
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <netdev.h>
+#include <linux/compiler.h>
+#include <asm/mmu.h>
+#include <asm/processor.h>
+#include <asm/cache.h>
+#include <asm/immap_85xx.h>
+#include <asm/fsl_law.h>
+#include <asm/fsl_serdes.h>
+#include <asm/fsl_portals.h>
+#include <asm/fsl_liodn.h>
+#include <fm_eth.h>
+
+#include "../common/qixis.h"
+#include "../common/vsc3316_3308.h"
+#include "b4860qds.h"
+#include "b4860qds_qixis.h"
+#include "b4860qds_crossbar_con.h"
+
+#define CLK_MUX_SEL_MASK	0x4
+#define ETH_PHY_CLK_OUT		0x4
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	u8 sw;
+	struct cpu_type *cpu = gd->cpu;
+	ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
+	unsigned int i;
+	static const char *const freq[] = {"100", "125", "156.25", "161.13",
+						"122.88", "122.88", "122.88"};
+	int clock;
+
+	printf("Board: %sDS, ", cpu->name);
+	printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\nFPGA Rev: 0x%02x, ",
+		QIXIS_READ(id), QIXIS_READ(arch), QIXIS_READ(scver));
+
+	printf("FPGA Ver: ");
+	for (i = 16; i < 34; i++) {
+		QIXIS_WRITE(tagdata, i);
+		printf("%c", QIXIS_READ(tagdata));
+	}
+
+	sw = QIXIS_READ(brdcfg[0]);
+	sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+	printf(", ");
+	if (sw < 0x8)
+		printf("vBank: %d\n", sw);
+	else if (sw >= 0x8 && sw <= 0xE)
+		puts("NAND\n");
+	else
+		printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+	/* Display the RCW, so that no one gets confused as to what RCW
+	 * we're actually using for this boot.
+	 */
+	puts("Reset Configuration Word (RCW):");
+	for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
+		u32 rcw = in_be32(&gur->rcwsr[i]);
+
+		if ((i % 4) == 0)
+			printf("\n       %08x:", i * 4);
+		printf(" %08x", rcw);
+	}
+	puts("\n");
+
+	/*
+	 * Display the actual SERDES reference clocks as configured by the
+	 * dip switches on the board.  Note that the SWx registers could
+	 * technically be set to force the reference clocks to match the
+	 * values that the SERDES expects (or vice versa).  For now, however,
+	 * we just display both values and hope the user notices when they
+	 * don't match.
+	 */
+	puts("SERDES Reference Clocks: ");
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = (sw >> 5) & 7;
+	printf("Bank1=%sMHz ", freq[clock]);
+	sw = QIXIS_READ(brdcfg[4]);
+	clock = (sw >> 6) & 3;
+	printf("Bank2=%sMHz\n", freq[clock]);
+
+	return 0;
+}
+
+int select_i2c_ch_pca(u8 ch)
+{
+	int ret;
+
+	/* Selecting proper channel via PCA*/
+	ret = i2c_write(I2C_MUX_PCA_ADDR, 0x0, 1, &ch, 1);
+	if (ret) {
+		printf("PCA: failed to select proper channel.\n");
+		return ret;
+	}
+
+	return 0;
+}
+
+int configure_vsc3316_3308(void)
+{
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	unsigned int num_vsc16_con, num_vsc08_con;
+	u32 serdes1_prtcl, serdes2_prtcl;
+	int ret;
+
+	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	if (!serdes1_prtcl) {
+		printf("SERDES1 is not enabled\n");
+		return 0;
+	}
+	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+			FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	if (!serdes2_prtcl) {
+		printf("SERDES2 is not enabled\n");
+		return 0;
+	}
+	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+	switch (serdes1_prtcl) {
+	case 0x2a:
+			/*
+			 * Configuration:
+			 * SERDES: 1
+			 * Lanes: A,B: SGMII
+			 * Lanes: C,D,E,F,G,H: CPRI
+			 */
+		debug("Configuring crossbar to use onboard SGMII PHYs:"
+				"srds_prctl:%x\n", serdes1_prtcl);
+		num_vsc16_con = NUM_CON_VSC3316;
+		/* Configure VSC3316 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+		if (!ret) {
+			ret = vsc3316_config(VSC3316_TX_ADDRESS,
+					vsc16_tx_sgmii, num_vsc16_con);
+			if (ret)
+				return ret;
+			ret = vsc3316_config(VSC3316_RX_ADDRESS,
+					vsc16_rx_sgmii, num_vsc16_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+
+
+	case 0x3E:      /* AMC */
+		num_vsc16_con = NUM_CON_VSC3316;
+		/* Configure VSC3316 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3316);
+		if (!ret) {
+			ret = vsc3316_config(VSC3316_TX_ADDRESS,
+					vsc16_tx_amc, num_vsc16_con);
+			if (ret)
+				return ret;
+			ret = vsc3316_config(VSC3316_RX_ADDRESS,
+					vsc16_rx_amc, num_vsc16_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+	default:
+		printf("WARNING:VSC crossbars programming not supported for:%x"
+					" SerDes1 Protocol.\n", serdes1_prtcl);
+		return -1;
+	}
+
+	switch (serdes2_prtcl) {
+	case 0x9E:
+	case 0x9A:
+		num_vsc08_con = NUM_CON_VSC3308;
+		/* Configure VSC3308 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3308);
+		if (!ret) {
+			ret = vsc3308_config(VSC3308_TX_ADDRESS,
+					vsc08_tx_amc, num_vsc08_con);
+			if (ret)
+				return ret;
+			ret = vsc3308_config(VSC3308_RX_ADDRESS,
+					vsc08_rx_amc, num_vsc08_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+	case 0x4E:
+		num_vsc08_con = NUM_CON_VSC3308;
+		/* Configure VSC3308 crossbar switch */
+		ret = select_i2c_ch_pca(I2C_CH_VSC3308);
+		if (!ret) {
+			ret = vsc3308_config(VSC3308_TX_ADDRESS,
+						vsc08_tx_sfp, num_vsc08_con);
+			if (ret)
+				return ret;
+			ret = vsc3308_config(VSC3308_RX_ADDRESS,
+						vsc08_rx_sfp, num_vsc08_con);
+			if (ret)
+				return ret;
+		} else {
+			return ret;
+		}
+		break;
+	default:
+		printf("WARNING:VSC crossbars programming not supported for: %x"
+					" SerDes2 Protocol.\n", serdes2_prtcl);
+		return -1;
+	}
+
+	return 0;
+}
+
+int board_early_init_r(void)
+{
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
+	const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
+
+	/*
+	 * Remap Boot flash + PROMJET region to caching-inhibited
+	 * so that flash can be erased properly.
+	 */
+
+	/* Flush d-cache and invalidate i-cache of any FLASH data */
+	flush_dcache();
+	invalidate_icache();
+
+	/* invalidate existing TLB entry for flash + promjet */
+	disable_tlb(flash_esel);
+
+	set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, flash_esel, BOOKE_PAGESZ_256M, 1);
+
+	set_liodns();
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	setup_portals();
+#endif
+
+	/* Configure VSC3316 and VSC3308 crossbar switches */
+	if (configure_vsc3316_3308())
+		printf("VSC:failed to configure VSC3316/3308.\n");
+	else
+		printf("VSC:VSC3316/3308 successfully configured.\n");
+
+	select_i2c_ch_pca(I2C_CH_DEFAULT);
+
+	return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+	u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch (sysclk_conf & 0x0F) {
+	case QIXIS_SYSCLK_83:
+		return 83333333;
+	case QIXIS_SYSCLK_100:
+		return 100000000;
+	case QIXIS_SYSCLK_125:
+		return 125000000;
+	case QIXIS_SYSCLK_133:
+		return 133333333;
+	case QIXIS_SYSCLK_150:
+		return 150000000;
+	case QIXIS_SYSCLK_160:
+		return 160000000;
+	case QIXIS_SYSCLK_166:
+		return 166666666;
+	}
+	return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+	u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+	switch ((ddrclk_conf & 0x30) >> 4) {
+	case QIXIS_DDRCLK_100:
+		return 100000000;
+	case QIXIS_DDRCLK_125:
+		return 125000000;
+	case QIXIS_DDRCLK_133:
+		return 133333333;
+	}
+	return 66666666;
+}
+
+static int serdes_refclock(u8 sw, u8 sdclk)
+{
+	unsigned int clock;
+	u32 ret = -1;
+	u8 brdcfg4;
+
+	if (sdclk == 1) {
+		brdcfg4 = QIXIS_READ(brdcfg[4]);
+		if ((brdcfg4 & CLK_MUX_SEL_MASK) == ETH_PHY_CLK_OUT)
+			return SRDS_PLLCR0_RFCK_SEL_125;
+		else
+			clock = (sw >> 5) & 7;
+	} else
+		clock = (sw >> 6) & 3;
+
+	switch (clock) {
+	case 0:
+		ret = SRDS_PLLCR0_RFCK_SEL_100;
+		break;
+	case 1:
+		ret = SRDS_PLLCR0_RFCK_SEL_125;
+		break;
+	case 2:
+		ret = SRDS_PLLCR0_RFCK_SEL_156_25;
+		break;
+	case 3:
+		ret = SRDS_PLLCR0_RFCK_SEL_161_13;
+		break;
+	case 4:
+	case 5:
+	case 6:
+		ret = SRDS_PLLCR0_RFCK_SEL_122_88;
+		break;
+	default:
+		ret = -1;
+		break;
+	}
+
+	return ret;
+}
+
+static const char *serdes_clock_to_string(u32 clock)
+{
+	switch (clock) {
+	case SRDS_PLLCR0_RFCK_SEL_100:
+		return "100";
+	case SRDS_PLLCR0_RFCK_SEL_125:
+		return "125";
+	case SRDS_PLLCR0_RFCK_SEL_156_25:
+		return "156.25";
+	case SRDS_PLLCR0_RFCK_SEL_161_13:
+		return "161.13";
+	default:
+		return "122.88";
+	}
+}
+
+#define NUM_SRDS_BANKS	2
+
+int misc_init_r(void)
+{
+	u8 sw;
+	serdes_corenet_t *srds_regs =
+		(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
+	u32 actual[NUM_SRDS_BANKS];
+	unsigned int i;
+	int clock;
+
+	sw = QIXIS_READ(brdcfg[2]);
+	clock = serdes_refclock(sw, 1);
+	if (clock >= 0)
+		actual[0] = clock;
+	else
+		printf("Warning: SDREFCLK1 switch setting is unsupported\n");
+
+	sw = QIXIS_READ(brdcfg[4]);
+	clock = serdes_refclock(sw, 2);
+	if (clock >= 0)
+		actual[1] = clock;
+	else
+		printf("Warning: SDREFCLK2 switch setting unsupported\n");
+
+	for (i = 0; i < NUM_SRDS_BANKS; i++) {
+		u32 pllcr0 = srds_regs->bank[i].pllcr0;
+		u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK;
+		if (expected != actual[i]) {
+			printf("Warning: SERDES bank %u expects reference clock"
+			       " %sMHz, but actual is %sMHz\n", i + 1,
+			       serdes_clock_to_string(expected),
+			       serdes_clock_to_string(actual[i]));
+		}
+	}
+
+	return 0;
+}
+
+void ft_board_setup(void *blob, bd_t *bd)
+{
+	phys_addr_t base;
+	phys_size_t size;
+
+	ft_cpu_setup(blob, bd);
+
+	base = getenv_bootm_low();
+	size = getenv_bootm_size();
+
+	fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_PCI
+	pci_of_setup(blob, bd);
+#endif
+
+	fdt_fixup_liodn(blob);
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+	fdt_fixup_dr_usb(blob, bd);
+#endif
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+	fdt_fixup_fman_ethernet(blob);
+	fdt_fixup_board_enet(blob);
+#endif
+}
diff --git a/board/freescale/b4860qds/b4860qds.h b/board/freescale/b4860qds/b4860qds.h
new file mode 100644
index 0000000..f290f3c
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds.h
@@ -0,0 +1,26 @@ 
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CORENET_DS_H__
+#define __CORENET_DS_H__
+
+void fdt_fixup_board_enet(void *blob);
+void pci_of_setup(void *blob, bd_t *bd);
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_crossbar_con.h b/board/freescale/b4860qds/b4860qds_crossbar_con.h
new file mode 100644
index 0000000..f23929b
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds_crossbar_con.h
@@ -0,0 +1,58 @@ 
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CROSSBAR_CONNECTIONS_H__
+#define __CROSSBAR_CONNECTIONS_H__
+
+#define NUM_CON_VSC3316	8
+#define NUM_CON_VSC3308	4
+
+static const int8_t vsc16_tx_amc[8][2] = { {15, 3}, {0, 2}, {7, 4}, {9, 10},
+				{5, 11}, {4, 5}, {2, 6}, {12, 9} };
+
+static const int8_t vsc16_tx_sfp[8][2] = { {15, 8}, {0, 0}, {7, 7}, {9, 1},
+				{5, 15}, {4, 14}, {2, 12}, {12, 13} };
+
+static const int8_t vsc16_tx_sgmii[8][2] = { {2, 14}, {12, 15}, {-1, -1},
+			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_tx_aurora[8][2] = { {2, 13}, {12, 12}, {-1, -1},
+			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_amc[8][2] = { {3, 15}, {2, 1}, {4, 8}, {10, 9},
+				{11, 11}, {5, 10}, {6, 3}, {9, 12} };
+
+static const int8_t vsc16_rx_sfp[8][2] = { {0, 15}, {8, 1}, {1, 8}, {7, 9},
+				{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_sgmii[8][2] = { {14, 3}, {15, 12}, {-1, -1},
+			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc16_rx_aurora[8][2] = { {12, 3}, {13, 12}, {-1, -1},
+			{-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1} };
+
+static const int8_t vsc08_tx_amc[4][2] = { {2, 2}, {3, 3}, {7, 4}, {1, 5} };
+
+static const int8_t vsc08_tx_sfp[4][2] = { {2, 6}, {3, 7}, {7, 1}, {1, 0} };
+
+static const int8_t vsc08_rx_amc[4][2] = { {2, 3}, {3, 4}, {4, 7}, {5, 1} };
+
+static const int8_t vsc08_rx_sfp[4][2] = { {6, 3}, {7, 4}, {1, 7}, {0, 1} };
+
+#endif
diff --git a/board/freescale/b4860qds/b4860qds_qixis.h b/board/freescale/b4860qds/b4860qds_qixis.h
new file mode 100644
index 0000000..175810d
--- /dev/null
+++ b/board/freescale/b4860qds/b4860qds_qixis.h
@@ -0,0 +1,47 @@ 
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __B4860QDS_QIXIS_H__
+#define __B4860QDS_QIXIS_H__
+
+/* Definitions of QIXIS Registers for B4860QDS */
+
+/* BRDCFG4[4:7]] select EC1 and EC2 as a pair */
+#define BRDCFG4_EMISEL_MASK		0xE0
+#define BRDCFG4_EMISEL_SHIFT		5
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66			0x0
+#define QIXIS_SYSCLK_83			0x1
+#define QIXIS_SYSCLK_100		0x2
+#define QIXIS_SYSCLK_125		0x3
+#define QIXIS_SYSCLK_133		0x4
+#define QIXIS_SYSCLK_150		0x5
+#define QIXIS_SYSCLK_160		0x6
+#define QIXIS_SYSCLK_166		0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66			0x0
+#define QIXIS_DDRCLK_100		0x1
+#define QIXIS_DDRCLK_125		0x2
+#define QIXIS_DDRCLK_133		0x3
+
+#define QIXIS_SRDS1CLK_122		0x5a
+#define QIXIS_SRDS1CLK_125		0x5e
+#endif
diff --git a/board/freescale/b4860qds/ddr.c b/board/freescale/b4860qds/ddr.c
new file mode 100644
index 0000000..dd4c0f6
--- /dev/null
+++ b/board/freescale/b4860qds/ddr.c
@@ -0,0 +1,190 @@ 
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * Version 2 or later as published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <hwconfig.h>
+#include <asm/mmu.h>
+#include <asm/fsl_ddr_sdram.h>
+#include <asm/fsl_ddr_dimm_params.h>
+#include <asm/fsl_law.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+dimm_params_t ddr_raw_timing = {
+	.n_ranks = 2,
+	.rank_density = 2147483648u,
+	.capacity = 4294967296u,
+	.primary_sdram_width = 64,
+	.ec_sdram_width = 8,
+	.registered_dimm = 0,
+	.mirrored_dimm = 1,
+	.n_row_addr = 15,
+	.n_col_addr = 10,
+	.n_banks_per_sdram_device = 8,
+	.edc_config = 2,	/* ECC */
+	.burst_lengths_bitmask = 0x0c,
+
+	.tCKmin_X_ps = 1071,
+	.caslat_X = 0x2fe << 4,	/* 5,6,7,8,9,10,11,13 */
+	.tAA_ps = 13910,
+	.tWR_ps = 15000,
+	.tRCD_ps = 13910,
+	.tRRD_ps = 6000,
+	.tRP_ps = 13910,
+	.tRAS_ps = 34000,
+	.tRC_ps = 48910,
+	.tRFC_ps = 260000,
+	.tWTR_ps = 7500,
+	.tRTP_ps = 7500,
+	.refresh_rate_ps = 7800000,
+	.tFAW_ps = 35000,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+		unsigned int controller_number,
+		unsigned int dimm_number)
+{
+	const char dimm_model[] = "RAW timing DDR";
+
+	if ((controller_number == 0) && (dimm_number == 0)) {
+		memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+		memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+		memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+	}
+
+	return 0;
+}
+
+struct board_specific_parameters {
+	u32 n_ranks;
+	u32 datarate_mhz_high;
+	u32 clk_adjust;
+	u32 wrlvl_start;
+	u32 wrlvl_ctl_2;
+	u32 wrlvl_ctl_3;
+	u32 cpo;
+	u32 write_data_delay;
+	u32 force_2T;
+};
+
+/*
+ * This table contains all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+static const struct board_specific_parameters udimm0[] = {
+	/*
+	 * memory controller 0
+	 *   num|  hi|  clk| wrlvl |   wrlvl   |  wrlvl | cpo  |wrdata|2T
+	 * ranks| mhz|adjst| start |   ctl2    |  ctl3  |      |delay |
+	 */
+	{2,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
+	{2,  1666,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
+	{2,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
+	{1,  1350,    4,     7, 0x09080807, 0x07060607,   0xff,    2,  0},
+	{1,  1700,    4,     7, 0x09080806, 0x06050607,   0xff,    2,  0},
+	{1,  1900,    3,     7, 0x08070706, 0x06040507,   0xff,    2,  0},
+	{}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+	udimm0,
+};
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+				dimm_params_t *pdimm,
+				unsigned int ctrl_num)
+{
+	const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+	ulong ddr_freq;
+
+	if (ctrl_num > 2) {
+		printf("Not supported controller number %d\n", ctrl_num);
+		return;
+	}
+	if (!pdimm->n_ranks)
+		return;
+
+	pbsp = udimms[0];
+
+
+	/* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
+	 * freqency and n_banks specified in board_specific_parameters table.
+	 */
+	ddr_freq = get_ddr_freq(0) / 1000000;
+	while (pbsp->datarate_mhz_high) {
+		if (pbsp->n_ranks == pdimm->n_ranks) {
+			if (ddr_freq <= pbsp->datarate_mhz_high) {
+				popts->cpo_override = pbsp->cpo;
+				popts->write_data_delay =
+					pbsp->write_data_delay;
+				popts->clk_adjust = pbsp->clk_adjust;
+				popts->wrlvl_start = pbsp->wrlvl_start;
+				popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+				popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+				popts->twoT_en = pbsp->force_2T;
+				goto found;
+			}
+			pbsp_highest = pbsp;
+		}
+		pbsp++;
+	}
+
+	if (pbsp_highest) {
+		printf("Error: board specific timing not found "
+			"for data rate %lu MT/s\n"
+			"Trying to use the highest speed (%u) parameters\n",
+			ddr_freq, pbsp_highest->datarate_mhz_high);
+		popts->cpo_override = pbsp_highest->cpo;
+		popts->write_data_delay = pbsp_highest->write_data_delay;
+		popts->clk_adjust = pbsp_highest->clk_adjust;
+		popts->wrlvl_start = pbsp_highest->wrlvl_start;
+		popts->twoT_en = pbsp_highest->force_2T;
+	} else {
+		panic("DIMM is not supported by this board");
+	}
+found:
+	/*
+	 * Factors to consider for half-strength driver enable:
+	 *	- number of DIMMs installed
+	 */
+	popts->half_strength_driver_enable = 0;
+	/*
+	 * Write leveling override
+	 */
+	popts->wrlvl_override = 1;
+	popts->wrlvl_sample = 0xf;
+
+	/*
+	 * Rtt and Rtt_WR override
+	 */
+	popts->rtt_override = 0;
+
+	/* Enable ZQ calibration */
+	popts->zq_en = 1;
+
+	/* DHC_EN =1, ODT = 75 Ohm */
+	popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
+	popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
+}
+
+phys_size_t initdram(int board_type)
+{
+	phys_size_t dram_size;
+
+	puts("Initializing....using SPD\n");
+
+	dram_size = fsl_ddr_sdram();
+
+	dram_size = setup_ddr_tlbs(dram_size / 0x100000);
+	dram_size *= 0x100000;
+
+	puts("    DDR: ");
+	return dram_size;
+}
diff --git a/board/freescale/b4860qds/eth_b4860qds.c b/board/freescale/b4860qds/eth_b4860qds.c
new file mode 100644
index 0000000..d87cb15
--- /dev/null
+++ b/board/freescale/b4860qds/eth_b4860qds.c
@@ -0,0 +1,287 @@ 
+/*
+ * Copyright 2012 Freescale Semiconductor, Inc.
+ * Author: Sandeep Kumar Singh <sandeep@freescale.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/* This file is based on board/freescale/corenet_ds/eth_superhydra.c */
+
+/*
+ * This file handles the board muxing between the Fman Ethernet MACs and
+ * the RGMII/SGMII/XGMII PHYs on a Freescale B4860 "Centaur". The SGMII
+ * PHYs are the two on-board 1Gb ports. There are no RGMII PHY on board.
+ * The 10Gb XGMII PHY is provided via the XAUI riser card. There is only
+ * one Fman device on B4860. The SERDES configuration is used to determine
+ * where the SGMII and XAUI cards exist, and also which Fman MACs are routed
+ * to which PHYs. So for a given Fman MAC, there is one and only PHY it
+ * connects to. MACs cannot be routed to PHYs dynamically. This configuration
+ * is done at boot time by reading SERDES protocol from RCW.
+ */
+
+#include <common.h>
+#include <netdev.h>
+#include <asm/fsl_serdes.h>
+#include <fm_eth.h>
+#include <fsl_mdio.h>
+#include <malloc.h>
+#include <fdt_support.h>
+#include <asm/fsl_dtsec.h>
+
+#include "../common/ngpixis.h"
+#include "../common/fman.h"
+#include "../common/qixis.h"
+#include "b4860qds_qixis.h"
+
+#define EMI_NONE       0xFFFFFFFF
+
+#ifdef CONFIG_FMAN_ENET
+
+/*
+ * Mapping of all 16 SERDES lanes to board slots. A value n(>0) will mean that
+ * lane at index is mapped to slot number n. A value of '0' will mean
+ * that the mapping must be determined dynamically, or that the lane maps to
+ * something other than a board slot
+ */
+static u8 lane_to_slot[] = {
+	0, 0, 0, 0,
+	0, 0, 0, 0,
+	1, 1, 1, 1,
+	0, 0, 0, 0
+};
+
+/*
+ * This function initializes the lane_to_slot[] array. It reads RCW to check
+ * if Serdes2{E,F,G,H} is configured as slot 2 or as SFP and initializes
+ * lane_to_slot[] accordingly
+ */
+static void initialize_lane_to_slot(void)
+{
+	unsigned int  serdes2_prtcl;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	debug("Initializing lane to slot: Serdes2 protocol: %x\n",
+			serdes2_prtcl);
+
+	switch (serdes2_prtcl) {
+	case 0x18:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: SGMII
+		 * Lanes: E,F: Aur
+		 * Lanes: G,H: SRIO
+		 */
+	case 0x91:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B: SGMII
+		 * Lanes: C,D: SRIO2
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0x93:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: SGMII
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0x98:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: XAUI2
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0x9a:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B: PCI
+		 * Lanes: C,D: SGMII
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0x9e:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B,C,D: PCI
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+	case 0xc2:
+		/*
+		 * Configuration:
+		 * SERDES: 2
+		 * Lanes: A,B: SGMII
+		 * Lanes: C,D: SRIO2
+		 * Lanes: E,F,G,H: XAUI2
+		 */
+		lane_to_slot[12] = 2;
+		lane_to_slot[13] = lane_to_slot[12];
+		lane_to_slot[14] = lane_to_slot[12];
+		lane_to_slot[15] = lane_to_slot[12];
+		break;
+
+	default:
+		printf("Fman: Unsupported SerDes2 Protocol 0x%02x\n",
+				serdes2_prtcl);
+			break;
+	}
+	return;
+}
+
+#endif /* #ifdef CONFIG_FMAN_ENET */
+
+int board_eth_init(bd_t *bis)
+{
+#ifdef CONFIG_FMAN_ENET
+	struct memac_mdio_info memac_mdio_info;
+	struct memac_mdio_info tg_memac_mdio_info;
+	unsigned int i;
+	unsigned int  serdes1_prtcl, serdes2_prtcl;
+	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	serdes1_prtcl = in_be32(&gur->rcwsr[4]) &
+		FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
+	if (!serdes1_prtcl) {
+		printf("SERDES1 is not enabled\n");
+		return 0;
+	}
+	serdes1_prtcl >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
+	debug("Using SERDES1 Protocol: 0x%x:\n", serdes1_prtcl);
+
+	serdes2_prtcl = in_be32(&gur->rcwsr[4]) &
+		FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
+	if (!serdes2_prtcl) {
+		printf("SERDES2 is not enabled\n");
+		return 0;
+	}
+	serdes2_prtcl >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
+	debug("Using SERDES2 Protocol: 0x%x:\n", serdes2_prtcl);
+
+	printf("Initializing Fman\n");
+
+	initialize_lane_to_slot();
+
+	memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
+	memac_mdio_info.name = DEFAULT_FM_MDIO_NAME;
+
+	/* Register the real 1G MDIO bus */
+	fm_memac_mdio_init(bis, &memac_mdio_info);
+
+	tg_memac_mdio_info.regs =
+		(struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
+	tg_memac_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
+
+	/* Register the real 10G MDIO bus */
+	fm_memac_mdio_init(bis, &tg_memac_mdio_info);
+
+	/*
+	 * Program the two on board DTSEC PHY addresses assuming that they are
+	 * all SGMII. RGMII is not supported on this board. Setting SGMII 5 and
+	 * 6 to on board SGMII phys
+	 */
+	fm_info_set_phy_address(FM1_DTSEC5, CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+	fm_info_set_phy_address(FM1_DTSEC6, CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+
+	switch (serdes1_prtcl) {
+	case 0x2a:
+		/* Serdes 1: A-B SGMII, Configuring DTSEC 5 and 6 */
+		debug("Setting phy addresses for FM1_DTSEC5: %x and"
+			"FM1_DTSEC6: %x\n", CONFIG_SYS_FM1_DTSEC5_PHY_ADDR,
+			CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+		/* Fixing Serdes clock by programming FPGA register */
+		QIXIS_WRITE(brdcfg[4], QIXIS_SRDS1CLK_125);
+		fm_info_set_phy_address(FM1_DTSEC5,
+				CONFIG_SYS_FM1_DTSEC5_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC6,
+				CONFIG_SYS_FM1_DTSEC6_PHY_ADDR);
+		break;
+	default:
+		printf("Fman:  Unsupported SerDes1 Protocol 0x%02x\n",
+				serdes1_prtcl);
+		break;
+	}
+	switch (serdes2_prtcl) {
+	case 0x18:
+		debug("Setting phy addresses on SGMII Riser card for"
+				"FM1_DTSEC1: %x\n",
+				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC1,
+				CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC2,
+				CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC3,
+				CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR);
+		fm_info_set_phy_address(FM1_DTSEC4,
+				CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR);
+		break;
+
+	default:
+		printf("Fman:  Unsupported SerDes2 Protocol 0x%02x\n",
+				serdes2_prtcl);
+		break;
+	}
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		int idx = i - FM1_DTSEC1;
+
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			fm_info_set_mdio(i,
+				miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
+			break;
+		case PHY_INTERFACE_MODE_NONE:
+			fm_info_set_phy_address(i, 0);
+			break;
+		default:
+			printf("Fman1: DTSEC%u set to unknown interface %i\n",
+					idx + 1, fm_info_get_enet_if(i));
+			fm_info_set_phy_address(i, 0);
+			break;
+		}
+	}
+
+	cpu_eth_init(bis);
+#endif
+
+	return pci_eth_init(bis);
+}
+
+/*
+ * tbd:Fixup function not doing any fixup right now.
+ */
+
+void fdt_fixup_board_enet(void *fdt)
+{
+	int i, idx;
+
+	for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
+		idx = i - FM1_DTSEC1;
+		switch (fm_info_get_enet_if(i)) {
+		case PHY_INTERFACE_MODE_SGMII:
+			break;
+		default:
+			break;
+		}
+	}
+}
diff --git a/board/freescale/b4860qds/law.c b/board/freescale/b4860qds/law.c
new file mode 100644
index 0000000..bfdd3f5
--- /dev/null
+++ b/board/freescale/b4860qds/law.c
@@ -0,0 +1,44 @@ 
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/fsl_law.h>
+#include <asm/mmu.h>
+
+struct law_entry law_table[] = {
+	SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_BMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_BMAN),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_LAW(CONFIG_SYS_QMAN_MEM_PHYS, LAW_SIZE_32M, LAW_TRGT_IF_QMAN),
+#endif
+	SET_LAW(QIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC),
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_LAW(CONFIG_SYS_DCSRBAR_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_DCSR),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE_PHYS
+	SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC),
+#endif
+};
+
+int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/b4860qds/pci.c b/board/freescale/b4860qds/pci.c
new file mode 100644
index 0000000..b130d13
--- /dev/null
+++ b/board/freescale/b4860qds/pci.c
@@ -0,0 +1,39 @@ 
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <command.h>
+#include <pci.h>
+#include <asm/fsl_pci.h>
+#include <libfdt.h>
+#include <fdt_support.h>
+#include <asm/fsl_serdes.h>
+
+void pci_init_board(void)
+{
+	fsl_pcie_init_board(0);
+}
+
+void pci_of_setup(void *blob, bd_t *bd)
+{
+	FT_FSL_PCI_SETUP;
+}
diff --git a/board/freescale/b4860qds/tlb.c b/board/freescale/b4860qds/tlb.c
new file mode 100644
index 0000000..7c5d8e0
--- /dev/null
+++ b/board/freescale/b4860qds/tlb.c
@@ -0,0 +1,122 @@ 
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/mmu.h>
+
+struct fsl_e_tlb_entry tlb_table[] = {
+	/* TLB 0 - for temp stack in cache */
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		      CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 0, BOOKE_PAGESZ_4K, 0),
+
+	/* TLB 1 */
+	/* *I*** - Covers boot page */
+#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
+	/*
+	 * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
+	 * SRAM is at 0xfff00000, it covered the 0xfffff000.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 0, BOOKE_PAGESZ_1M, 1),
+#else
+	SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 0, BOOKE_PAGESZ_4K, 1),
+#endif
+
+	/* *I*G* - CCSRBAR */
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 1, BOOKE_PAGESZ_16M, 1),
+
+	/* *I*G* - Flash, localbus */
+	/* This will be changed to *I*G* after relocation to RAM. */
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+		      MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+		      0, 2, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 3, BOOKE_PAGESZ_256M, 1),
+
+	/* *I*G* - PCI I/O */
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 4, BOOKE_PAGESZ_64K, 1),
+
+	/* Bman/Qman */
+#ifdef CONFIG_SYS_BMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 5, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_BMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 6, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_QMAN_MEM_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
+		      0, 7, BOOKE_PAGESZ_16M, 1),
+	SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x01000000,
+		      CONFIG_SYS_QMAN_MEM_PHYS + 0x01000000,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 8, BOOKE_PAGESZ_16M, 1),
+#endif
+#ifdef CONFIG_SYS_DCSRBAR_PHYS
+	SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 9, BOOKE_PAGESZ_4M, 1),
+#endif
+#ifdef CONFIG_SYS_NAND_BASE
+	/*
+	 * *I*G - NAND
+	 * entry 14 and 15 has been used hard coded, they will be disabled
+	 * in cpu_init_f, so we use entry 16 for nand.
+	 */
+	SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+			MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+			0, 10, BOOKE_PAGESZ_1M, 1),
+#endif
+	SET_TLB_ENTRY(1, QIXIS_BASE, QIXIS_BASE_PHYS,
+		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+		      0, 11, BOOKE_PAGESZ_4K, 1),
+
+};
+
+int num_tlb_entries = ARRAY_SIZE(tlb_table);
diff --git a/boards.cfg b/boards.cfg
index 06b0ec3..b0b1edf 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -834,6 +834,8 @@  stxssa_4M                    powerpc     mpc85xx     stxssa              stx
 T4240QDS                     powerpc     mpc85xx     t4qds               freescale
 T4240QDS_SDCARD              powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF80000
 T4240QDS_SPIFLASH            powerpc     mpc85xx     t4qds               freescale	-           T4240QDS:RAMBOOT_PBL,SPIFLASH,SYS_TEXT_BASE=0xFFF80000
+B4860QDS                     powerpc     mpc85xx     b4860qds            freescale
+B4860QDS_NAND		     powerpc     mpc85xx     b4860qds            freescale      -           B4860QDS:RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF80000
 TQM8540                      powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8540,TQM8540=y,HOSTNAME=tqm8540,BOARDNAME="TQM8540"
 TQM8541                      powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8541,TQM8541=y,HOSTNAME=tqm8541,BOARDNAME="TQM8541"
 TQM8548                      powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8548,TQM8548=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548"
diff --git a/doc/README.b4860qds b/doc/README.b4860qds
new file mode 100644
index 0000000..2929592
--- /dev/null
+++ b/doc/README.b4860qds
@@ -0,0 +1,20 @@ 
+Overview
+--------
+The B4860QDS is a Freescale reference board that hosts the B4860 SoC (and variants).
+
+Memory map
+----------
+The addresses in brackets are physical addresses.
+
+0x0_0000_0000 (0x0_0000_0000) - 0x0_7fff_ffff   2GB DDR (more than 2GB is initialized but not mapped under with TLB)
+0x0_8000_0000 (0xc_0000_0000) - 0x0_8fff_ffff 512MB PCIE memory
+0x0_f000_0000 (0xf_0000_0000) - 0x0_f03f_ffff  4MB  DCSR
+0x0_f400_0000 (0xf_f400_0000) - 0x0_f5ff_ffff  32MB BMan
+0x0_f600_0000 (0xf_f500_0000) - 0x0_f7ff_ffff  32MB QMan
+0x0_f800_0000 (0xf_f800_0000) - 0x0_f800_ffff  64KB PCIE IO
+0x0_e000_0000 (0xf_e000_0000) - 0x0_efff_ffff 256MB NOR flash
+0x0_fe00_0000 (0xf_fe00_0000) - 0x0_feff_ffff  16MB CCSR
+0x0_ffdf_0000 (0xf_ffdf_0000) - 0x0_ffdf_03ff   4KB QIXIS
+0x0_ffff_f000 (0x0_7fff_fff0) - 0x0_ffff_ffff   4KB Boot page translation for secondary cores
+
+The physical address of the last (boot page translation) varies with the actual DDR size.
diff --git a/include/configs/B4860QDS.h b/include/configs/B4860QDS.h
new file mode 100644
index 0000000..64b46b2
--- /dev/null
+++ b/include/configs/B4860QDS.h
@@ -0,0 +1,812 @@ 
+/*
+ * Copyright 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * B4860 QDS board configuration file
+ */
+#define CONFIG_B4860QDS
+#define CONFIG_PHYS_64BIT
+#define CONFIG_PPC_B4860
+
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_RAMBOOT_TEXT_BASE	CONFIG_SYS_TEXT_BASE
+#define CONFIG_RESET_VECTOR_ADDRESS	0xfffffffc
+#endif
+
+/* High Level Configuration Options */
+#define CONFIG_BOOKE
+#define CONFIG_E6500
+#define CONFIG_E500			/* BOOKE e500 family */
+#define CONFIG_E500MC			/* BOOKE e500mc family */
+#define CONFIG_SYS_BOOK3E_HV		/* Category E.HV supported */
+#define CONFIG_MPC85xx			/* MPC85xx/PQ3 platform */
+#define CONFIG_FSL_CORENET		/* Freescale CoreNet platform */
+#define CONFIG_MP			/* support multiple processors */
+
+#ifndef CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_TEXT_BASE	0xeff80000
+#endif
+
+#ifndef CONFIG_RESET_VECTOR_ADDRESS
+#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
+#endif
+
+#define CONFIG_SYS_FSL_CPC		/* Corenet Platform Cache */
+#define CONFIG_SYS_NUM_CPC		CONFIG_NUM_DDR_CONTROLLERS
+#define CONFIG_FSL_IFC			/* Enable IFC Support */
+#define CONFIG_PCI			/* Enable PCI/PCIE */
+#define CONFIG_PCIE1			/* PCIE controler 1 */
+#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
+#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */
+
+#define CONFIG_SYS_SRIO
+#define CONFIG_SRIO1			/* SRIO port 1 */
+#define CONFIG_SRIO2			/* SRIO port 2 */
+
+#define CONFIG_FSL_LAW			/* Use common FSL init code */
+
+/* I2C bus multiplexer */
+#define I2C_MUX_PCA_ADDR                0x77
+
+/* VSC Crossbar switches */
+#define CONFIG_VSC_CROSSBAR
+#define I2C_CH_DEFAULT                  0x8
+#define I2C_CH_VSC3316                  0xc
+#define I2C_CH_VSC3308                  0xd
+
+#define VSC3316_TX_ADDRESS              0x70
+#define VSC3316_RX_ADDRESS              0x71
+#define VSC3308_TX_ADDRESS              0x02
+#define VSC3308_RX_ADDRESS              0x03
+
+#define CONFIG_ENV_OVERWRITE
+
+#ifdef CONFIG_SYS_NO_FLASH
+#define CONFIG_ENV_IS_NOWHERE
+#else
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#endif
+
+#ifndef CONFIG_SYS_NO_FLASH
+#if defined(CONFIG_SPIFLASH)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_SPI_FLASH
+#define CONFIG_ENV_SPI_BUS              0
+#define CONFIG_ENV_SPI_CS               0
+#define CONFIG_ENV_SPI_MAX_HZ           10000000
+#define CONFIG_ENV_SPI_MODE             0
+#define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
+#define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
+#define CONFIG_ENV_SECT_SIZE            0x10000
+#elif defined(CONFIG_SDCARD)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV          0
+#define CONFIG_ENV_SIZE			0x2000
+#define CONFIG_ENV_OFFSET		(512 * 1097)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_EXTRA_ENV_RELOC
+#define CONFIG_ENV_IS_IN_NAND
+#define CONFIG_ENV_SIZE			CONFIG_SYS_NAND_BLOCK_SIZE
+#define CONFIG_ENV_OFFSET		(5 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000 /* 128K (one sector) */
+#endif
+#else /* CONFIG_SYS_NO_FLASH */
+#define CONFIG_ENV_SIZE                0x2000
+#define CONFIG_ENV_SECT_SIZE   0x20000 /* 128K (one sector) */
+#endif
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk() /* sysclk for MPC85xx */
+#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
+
+/*
+ * These can be toggled for performance analysis, otherwise use default.
+ */
+#define CONFIG_SYS_CACHE_STASHING
+#define CONFIG_BTB			/* toggle branch predition */
+#define CONFIG_DDR_ECC
+#ifdef CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
+#endif
+
+#define CONFIG_ENABLE_36BIT_PHYS
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_ADDR_MAP
+#define CONFIG_SYS_NUM_ADDR_MAP		64	/* number of TLB1 entries */
+#endif
+
+#if 0
+#define CONFIG_POST CONFIG_SYS_POST_MEMORY	/* test POST memory test */
+#endif
+#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
+#define CONFIG_SYS_MEMTEST_END		0x00400000
+#define CONFIG_SYS_ALT_MEMTEST
+#define CONFIG_PANIC_HANG	/* do not reset board on panic */
+
+/*
+ *  Config the L3 Cache as L3 SRAM
+ */
+#define CONFIG_SYS_INIT_L3_ADDR		CONFIG_RAMBOOT_TEXT_BASE
+
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_DCSRBAR		0xf0000000
+#define CONFIG_SYS_DCSRBAR_PHYS		0xf00000000ull
+#endif
+
+/* EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM	0
+#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+/*
+ * DDR Setup
+ */
+#define CONFIG_VERY_BIG_RAM
+#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
+#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+
+/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
+#define CONFIG_DIMM_SLOTS_PER_CTLR	1
+#define CONFIG_CHIP_SELECTS_PER_CTRL	(4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_FSL_DDR3
+
+#define CONFIG_SYS_SPD_BUS_NUM	0
+#define SPD_EEPROM_ADDRESS1	0x51
+#define SPD_EEPROM_ADDRESS2	0x53
+
+#define SPD_EEPROM_ADDRESS	SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SDRAM_SIZE	2048	/* for fixed parameter use */
+
+/*
+ * IFC Definitions
+ */
+#define CONFIG_SYS_FLASH_BASE	0xe0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_FLASH_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_FLASH_BASE)
+#else
+#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#endif
+
+#define CONFIG_SYS_NOR0_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR0_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
+				+ 0x8000000) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NOR1_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
+				CSPR_PORT_SIZE_16 | \
+				CSPR_MSEL_NOR | \
+				CSPR_V)
+#define CONFIG_SYS_NOR_AMASK	IFC_AMASK(128*1024*1024)
+/* NOR Flash Timing Params */
+#define CONFIG_SYS_NOR_CSOR	CSOR_NOR_ADM_SHIFT(4)
+#define CONFIG_SYS_NOR_FTIM0	(FTIM0_NOR_TACSE(0x01) | \
+				FTIM0_NOR_TEADC(0x01) | \
+				FTIM0_NOR_TEAHC(0x20))
+#define CONFIG_SYS_NOR_FTIM1	(FTIM1_NOR_TACO(0x35) | \
+				FTIM1_NOR_TRAD_NOR(0x1A) |\
+				FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2	(FTIM2_NOR_TCS(0x01) | \
+				FTIM2_NOR_TCH(0x0E) | \
+				FTIM2_NOR_TWPH(0x0E) | \
+				FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3	0x0
+
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT	1024	/* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST	{CONFIG_SYS_FLASH_BASE_PHYS \
+					+ 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
+
+#define CONFIG_FSL_QIXIS	/* use common QIXIS code */
+#define CONFIG_FSL_QIXIS_V2
+#define QIXIS_BASE		0xffdf0000
+#ifdef CONFIG_PHYS_64BIT
+#define QIXIS_BASE_PHYS		(0xf00000000ull | QIXIS_BASE)
+#else
+#define QIXIS_BASE_PHYS		QIXIS_BASE
+#endif
+#define QIXIS_LBMAP_SWITCH		0x01
+#define QIXIS_LBMAP_MASK		0x0f
+#define QIXIS_LBMAP_SHIFT		0
+#define QIXIS_LBMAP_DFLTBANK		0x01
+#define QIXIS_LBMAP_ALTBANK		0x07
+#define QIXIS_RST_FRCE_PRST		0x01
+#define QIXIS_RCFG_CTL_UNLOCK		0x00
+#define QIXIS_RCFG_CTL_LOCK		0x10
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE	0x08
+
+#define CONFIG_SYS_CSPR3_EXT	(0xf)
+#define CONFIG_SYS_CSPR3	(CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 \
+				| CSPR_MSEL_GPCM \
+				| CSPR_V)
+#define CONFIG_SYS_AMASK3	IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3	0x0
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0		(FTIM0_GPCM_TACSE(0x0e) | \
+					FTIM0_GPCM_TEADC(0x0e) | \
+					FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1		(FTIM1_GPCM_TACO(0x0e) | \
+					FTIM1_GPCM_TRAD(0x1f))
+#define CONFIG_SYS_CS3_FTIM2		(FTIM2_GPCM_TCS(0x0e) | \
+					FTIM2_GPCM_TCH(0x0) | \
+					FTIM2_GPCM_TWP(0x1f))
+#define CONFIG_SYS_CS3_FTIM3		0x0
+
+/* NAND Flash on IFC */
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_BASE		0xff800000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_NAND_BASE_PHYS	(0xf00000000ull | CONFIG_SYS_NAND_BASE)
+#else
+#define CONFIG_SYS_NAND_BASE_PHYS	CONFIG_SYS_NAND_BASE
+#endif
+
+#define CONFIG_SYS_NAND_CSPR_EXT	(0xf)
+#define CONFIG_SYS_NAND_CSPR	(CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+				| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+				| CSPR_MSEL_NAND	/* MSEL = NAND */ \
+				| CSPR_V)
+#define CONFIG_SYS_NAND_AMASK	IFC_AMASK(64*1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+				| CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+				| CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+				| CSOR_NAND_RAL_3	/* RAL = 2Byes */ \
+				| CSOR_NAND_PGS_2K	/* Page Size = 2K */ \
+				| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+				| CSOR_NAND_PB(64))	/*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0		(FTIM0_NAND_TCCST(0x07) | \
+					FTIM0_NAND_TWP(0x18)   | \
+					FTIM0_NAND_TWCHT(0x07) | \
+					FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1		(FTIM1_NAND_TADLE(0x32) | \
+					FTIM1_NAND_TWBE(0x39)  | \
+					FTIM1_NAND_TRR(0x0e)   | \
+					FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2		(FTIM2_NAND_TRAD(0x0f) | \
+					FTIM2_NAND_TREH(0x0a) | \
+					FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3		0x0
+
+#define CONFIG_SYS_NAND_DDR_LAW		11
+
+#define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE	1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE	(128 * 1024)
+
+#if defined(CONFIG_NAND)
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NAND_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NOR_FTIM3
+#else
+#define CONFIG_SYS_CSPR0_EXT		CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0		CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3		CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT		CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2		CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2		CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2		CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0		CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1		CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2		CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3		CONFIG_SYS_NAND_FTIM3
+#endif
+#define CONFIG_SYS_CSPR1_EXT		CONFIG_SYS_NOR1_CSPR_EXT
+#define CONFIG_SYS_CSPR1		CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1		CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1		CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0		CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1		CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2		CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3		CONFIG_SYS_NOR_FTIM3
+
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+
+#if defined(CONFIG_RAMBOOT_PBL)
+#define CONFIG_SYS_RAMBOOT
+#endif
+
+#define CONFIG_BOARD_EARLY_INIT_R
+#define CONFIG_MISC_INIT_R
+
+#define CONFIG_HWCONFIG
+
+/* define to use L1 as initial stack */
+#define CONFIG_L1_INIT_RAM
+#define CONFIG_SYS_INIT_RAM_LOCK
+#define CONFIG_SYS_INIT_RAM_ADDR	0xfdd00000	/* Initial L1 address */
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH	0xf
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW	0xfe0ec000
+/* The assembler doesn't like typecast */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
+	((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
+	  CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
+#else
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS	0xfe0ec000 /* Initial L1 address */
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
+#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
+#endif
+#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000
+
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - \
+					GENERATED_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
+
+/* Serial Port - controlled on board with jumper J8
+ * open - index 2
+ * shorted - index 1
+ */
+#define CONFIG_CONS_INDEX	1
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		(get_bus_freq(0)/2)
+
+#define CONFIG_SYS_BAUDRATE_TABLE	\
+	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
+
+#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x11C500)
+#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x11C600)
+#define CONFIG_SYS_NS16550_COM3	(CONFIG_SYS_CCSRBAR+0x11D500)
+#define CONFIG_SYS_NS16550_COM4	(CONFIG_SYS_CCSRBAR+0x11D600)
+#define CONFIG_SERIAL_MULTI		/* Enable both serial ports */
+#define CONFIG_SYS_CONSOLE_IS_IN_ENV	/* determine from environment */
+
+
+/* Use the HUSH parser */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+#define CONFIG_OF_STDOUT_VIA_ALIAS
+
+/* new uImage format support */
+#define CONFIG_FIT
+#define CONFIG_FIT_VERBOSE	/* enable fit_format_{error,warning}() */
+
+/* I2C */
+#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
+#define CONFIG_HARD_I2C		/* I2C with hardware support */
+#define CONFIG_I2C_MULTI_BUS
+#define CONFIG_I2C_CMD_TREE
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed in Hz */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_OFFSET		0x118000
+#define CONFIG_SYS_I2C2_OFFSET		0x119000
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/*
+ * RapidIO
+ */
+#define CONFIG_SYS_SRIO1_MEM_VIRT	0xa0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc20000000ull
+#else
+#define CONFIG_SYS_SRIO1_MEM_PHYS	0xa0000000
+#endif
+#define CONFIG_SYS_SRIO1_MEM_SIZE	0x10000000	/* 256M */
+
+#define CONFIG_SYS_SRIO2_MEM_VIRT	0xb0000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xc30000000ull
+#else
+#define CONFIG_SYS_SRIO2_MEM_PHYS	0xb0000000
+#endif
+#define CONFIG_SYS_SRIO2_MEM_SIZE	0x10000000	/* 256M */
+
+/*
+ * for slave u-boot IMAGE instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef080000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff80000ull
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x80000	/* 512K */
+#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff80000ull
+/*
+ * for slave UCODE and ENV instored in master memory space,
+ * PHYS must be aligned based on the SIZE
+ */
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef040000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000	/* 256K */
+
+/* slave core release by master*/
+#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+
+/*
+ * SRIO_PCIE_BOOT - SLAVE
+ */
+#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+		(0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#endif
+
+/*
+ * eSPI - Enhanced SPI
+ */
+#define CONFIG_FSL_ESPI
+#define CONFIG_SPI_FLASH
+#define CONFIG_SPI_FLASH_SST
+#define CONFIG_CMD_SF
+#define CONFIG_SF_DEFAULT_SPEED         10000000
+#define CONFIG_SF_DEFAULT_MODE          0
+
+/*
+ * General PCI
+ * Memory space is mapped 1-1, but I/O space must start from 0.
+ */
+
+/* controller 1, direct to uli, tgtid 3, Base address 20000 */
+#define CONFIG_SYS_PCIE1_MEM_VIRT	0x80000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc00000000ull
+#else
+#define CONFIG_SYS_PCIE1_MEM_BUS	0x80000000
+#define CONFIG_SYS_PCIE1_MEM_PHYS	0x80000000
+#endif
+#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CONFIG_SYS_PCIE1_IO_VIRT	0xf8000000
+#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xff8000000ull
+#else
+#define CONFIG_SYS_PCIE1_IO_PHYS	0xf8000000
+#endif
+#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */
+
+/* Qman/Bman */
+#ifndef CONFIG_NOBQFMAN
+#define CONFIG_SYS_DPAA_QBMAN		/* Support Q/Bman */
+#define CONFIG_SYS_BMAN_NUM_PORTALS	25
+#define CONFIG_SYS_BMAN_MEM_BASE	0xf4000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_BMAN_MEM_PHYS	0xff4000000ull
+#else
+#define CONFIG_SYS_BMAN_MEM_PHYS	CONFIG_SYS_BMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_BMAN_MEM_SIZE	0x02000000
+#define CONFIG_SYS_QMAN_NUM_PORTALS	25
+#define CONFIG_SYS_QMAN_MEM_BASE	0xf6000000
+#ifdef CONFIG_PHYS_64BIT
+#define CONFIG_SYS_QMAN_MEM_PHYS	0xff6000000ull
+#else
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
+#endif
+#define CONFIG_SYS_QMAN_MEM_SIZE	0x02000000
+
+#define CONFIG_SYS_DPAA_FMAN
+
+/* Default address of microcode for the Linux Fman driver */
+#if defined(CONFIG_SPIFLASH)
+/*
+ * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
+ * env, so we got 0x110000.
+ */
+#define CONFIG_SYS_QE_FW_IN_SPIFLASH
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	0x110000
+#elif defined(CONFIG_SDCARD)
+/*
+ * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
+ * about 545KB (1089 blocks), Env is stored after the image, and the env size is
+ * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
+ */
+#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(512 * 1130)
+#elif defined(CONFIG_NAND)
+#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#define CONFIG_SYS_QE_FMAN_FW_ADDR	(6 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#else
+#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
+#define CONFIG_SYS_QE_FMAN_FW_ADDR		0xEFF40000
+#endif
+#define CONFIG_SYS_QE_FMAN_FW_LENGTH	0x10000
+#define CONFIG_SYS_FDT_PAD		(0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
+#endif /* CONFIG_NOBQFMAN */
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+#define CONFIG_FMAN_ENET
+#define CONFIG_PHYLIB_10G
+#define CONFIG_PHY_VITESSE
+#define CONFIG_PHY_TERANETICS
+#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
+#define SGMII_CARD_PORT2_PHY_ADDR 0x10
+#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
+#define SGMII_CARD_PORT4_PHY_ADDR 0x11
+#endif
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP			/* do pci plug-and-play */
+#define CONFIG_E1000
+
+#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
+#define CONFIG_DOS_PARTITION
+#endif	/* CONFIG_PCI */
+
+#ifdef CONFIG_FMAN_ENET
+#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR	0x10
+#define CONFIG_SYS_FM1_DTSEC6_PHY_ADDR	0x11
+#define CONFIG_SYS_FM1_10GEC1_PHY_ADDR	4
+
+#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
+#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
+#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
+#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
+
+#define CONFIG_MII		/* MII PHY management */
+#define CONFIG_ETHPRIME		"FM1@DTSEC1"
+#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
+#endif
+
+/*
+ * Environment
+ */
+#define CONFIG_LOADS_ECHO		/* echo on for serial download */
+#define CONFIG_SYS_LOADS_BAUD_CHANGE	/* allow baudrate change */
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_ELF
+#define CONFIG_CMD_ERRATA
+#define CONFIG_CMD_GREPENV
+#define CONFIG_CMD_IRQ
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_PING
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SETEXPR
+
+#ifdef CONFIG_PCI
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+/*
+* USB
+*/
+#define CONFIG_HAS_FSL_DR_USB
+
+#ifdef CONFIG_HAS_FSL_DR_USB
+#define CONFIG_USB_EHCI
+
+#ifdef CONFIG_USB_EHCI
+#define CONFIG_CMD_USB
+#define CONFIG_USB_STORAGE
+#define CONFIG_USB_EHCI_FSL
+#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
+#define CONFIG_CMD_EXT2
+#endif
+#endif
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
+#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
+#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
+#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
+#else
+#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
+#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
+#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 64 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial map for Linux*/
+#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */
+
+#ifdef CONFIG_CMD_KGDB
+#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
+#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
+#endif
+
+/*
+ * Environment Configuration
+ */
+#define CONFIG_ROOTPATH		"/opt/nfsroot"
+#define CONFIG_BOOTFILE		"uImage"
+#define CONFIG_UBOOTPATH	"u-boot.bin"	/* U-Boot image on TFTP server*/
+
+/* default location for tftp and bootm */
+#define CONFIG_LOADADDR		1000000
+
+#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
+
+#define CONFIG_BAUDRATE	115200
+
+#define __USB_PHY_TYPE	ulpi
+
+#define	CONFIG_EXTRA_ENV_SETTINGS				\
+	"hwconfig=fsl_ddr:ctlr_intlv=cacheline,"		\
+	"bank_intlv=cs0_cs1;"					\
+	"usb1:dr_mode=host,phy_type=" MK_STR(__USB_PHY_TYPE) "\0"\
+	"netdev=eth0\0"						\
+	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"			\
+	"ubootaddr=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"			\
+	"tftpflash=tftpboot $loadaddr $uboot && "		\
+	"protect off $ubootaddr +$filesize && "			\
+	"erase $ubootaddr +$filesize && "			\
+	"cp.b $loadaddr $ubootaddr $filesize && "		\
+	"protect on $ubootaddr +$filesize && "			\
+	"cmp.b $loadaddr $ubootaddr $filesize\0"		\
+	"consoledev=ttyS0\0"					\
+	"ramdiskaddr=2000000\0"					\
+	"ramdiskfile=b4860qds/ramdisk.uboot\0"			\
+	"fdtaddr=c00000\0"					\
+	"fdtfile=b4860qds/b4860qds.dtb\0"				\
+	"bdev=sda3\0"						\
+	"c=ffe\0"
+
+/* For emulation this causes u-boot to jump to the start of the proof point
+   app code automatically */
+#define CONFIG_PROOF_POINTS			\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "cpu 1 release 0x29000000 - - -;"		\
+ "cpu 2 release 0x29000000 - - -;"		\
+ "cpu 3 release 0x29000000 - - -;"		\
+ "cpu 4 release 0x29000000 - - -;"		\
+ "cpu 5 release 0x29000000 - - -;"		\
+ "cpu 6 release 0x29000000 - - -;"		\
+ "cpu 7 release 0x29000000 - - -;"		\
+ "go 0x29000000"
+
+#define CONFIG_HVBOOT	\
+ "setenv bootargs config-addr=0x60000000; "	\
+ "bootm 0x01000000 - 0x00f00000"
+
+#define CONFIG_ALU				\
+ "setenv bootargs root=/dev/$bdev rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "cpu 1 release 0x01000000 - - -;"		\
+ "cpu 2 release 0x01000000 - - -;"		\
+ "cpu 3 release 0x01000000 - - -;"		\
+ "cpu 4 release 0x01000000 - - -;"		\
+ "cpu 5 release 0x01000000 - - -;"		\
+ "cpu 6 release 0x01000000 - - -;"		\
+ "cpu 7 release 0x01000000 - - -;"		\
+ "go 0x01000000"
+
+#define CONFIG_LINUX				\
+ "setenv bootargs root=/dev/ram rw "		\
+ "console=$consoledev,$baudrate $othbootargs;"	\
+ "setenv ramdiskaddr 0x02000000;"		\
+ "setenv fdtaddr 0x00c00000;"			\
+ "setenv loadaddr 0x1000000;"			\
+ "bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_HDBOOT					\
+	"setenv bootargs root=/dev/$bdev rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_NFSBOOTCOMMAND			\
+	"setenv bootargs root=/dev/nfs rw "	\
+	"nfsroot=$serverip:$rootpath "		\
+	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $loadaddr $bootfile;"		\
+	"tftp $fdtaddr $fdtfile;"		\
+	"bootm $loadaddr - $fdtaddr"
+
+#define CONFIG_RAMBOOTCOMMAND				\
+	"setenv bootargs root=/dev/ram rw "		\
+	"console=$consoledev,$baudrate $othbootargs;"	\
+	"tftp $ramdiskaddr $ramdiskfile;"		\
+	"tftp $loadaddr $bootfile;"			\
+	"tftp $fdtaddr $fdtfile;"			\
+	"bootm $loadaddr $ramdiskaddr $fdtaddr"
+
+#define CONFIG_BOOTCOMMAND		CONFIG_LINUX
+
+#ifdef CONFIG_SECURE_BOOT
+#include <asm/fsl_secure_boot.h>
+#endif
+
+#endif	/* __CONFIG_H */