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A new file (bdver3.md) is also attached which describes the pipelines. Presently, the tuning is copied mostly from its predecessor. However, the pipelines are modeled for the new core. "Make -k check" passes. Is it OK for upstream? Regards Ganesh 2012-10-11 Ganesh Gopalasubramanian bdver3 Enablement * gcc/doc/extend.texi: Add details about bdver3. * gcc/doc/invoke.texi: Add details about bdver3. * config.gcc (i[34567]86-*-linux* | ...): Add bdver3. (case ${target}): Add bdver3. * config/i386/i386.h (TARGET_BDVER3): New definition. * config/i386/i386.md (define_attr "cpu"): Add bdver3. * config/i386/cpuid.h (bit_XSAVEOPT): New field for getting the xsaveopt cpuid flag. * config/i386/sse.md (sseshuf): New instruction attribute added for identifying the shuffle instructions. * config/i386/i386.opt (flag_dispatch_scheduler): Add bdver3. * config/i386/i386-c.c (ix86_target_macros_internal): Add bdver3 def_and_undef * config/i386/driver-i386.c (host_detect_local_cpu): Let -march=native recognize bdver3 processors. * config/i386/i386.c (struct processor_costs btver2_cost): New bdver3 cost table. (m_BDVER3): New definition. (m_AMD_MULTIPLE): Includes m_BDVER3. (initial_ix86_tune_features): Add bdver3 tune. (processor_target_table): Add bdver3 entry. (static const char *const cpu_names): Add bdver3 entry. (software_prefetching_beneficial_p): Add bdver3. (ix86_option_override_internal): Add bdver3 instruction sets. (ix86_issue_rate): Add bdver3. (ix86_adjust_cost): Add bdver3. (enum target_cpu_default): Add TARGET_CPU_DEFAULT_bdver3. (enum processor_type): Add PROCESSOR_BDVER3. * config/i386/bdver3.md: New file describing bdver3 pipelines. Index: gcc/doc/extend.texi =================================================================== --- gcc/doc/extend.texi (revision 192031) +++ gcc/doc/extend.texi (working copy) @@ -9589,6 +9589,9 @@ @item bdver2 AMD family 15h Bulldozer version 2. +@item bdver3 +AMD family 15h Bulldozer version 3. + @item btver2 AMD family 16h CPU. @end table Index: gcc/doc/invoke.texi =================================================================== --- gcc/doc/invoke.texi (revision 192031) +++ gcc/doc/invoke.texi (working copy) @@ -13445,6 +13445,11 @@ supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set extensions.) +@item bdver3 +AMD Family 15h core based CPUs with x86-64 instruction set support. (This +supersets BMI, TBM, F16C, FMA, AVX, XOP, LWP, AES, PCL_MUL, CX16, MMX, SSE, +SSE2, SSE3, SSE4A, SSSE3, SSE4.1, SSE4.2, ABM and 64-bit instruction set +extensions.) @item btver1 CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This Index: gcc/config.gcc =================================================================== --- gcc/config.gcc (revision 192031) +++ gcc/config.gcc (working copy) @@ -1231,7 +1231,7 @@ TM_MULTILIB_CONFIG=`echo $TM_MULTILIB_CONFIG | sed 's/^,//'` need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1240,7 +1240,7 @@ ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1352,7 +1352,7 @@ tmake_file="$tmake_file i386/t-sol2-64" need_64bit_isa=yes case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1361,7 +1361,7 @@ ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 corei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -1418,7 +1418,7 @@ if test x$enable_targets = xall; then tm_defines="${tm_defines} TARGET_BI_ARCH=1" case X"${with_cpu}" in - Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) + Xgeneric|Xatom|Xcore2|Xcorei7|Xcorei7-avx|Xnocona|Xx86-64|Xbdver3|Xbdver2|Xbdver1|Xbtver2|Xbtver1|Xamdfam10|Xbarcelona|Xk8|Xopteron|Xathlon64|Xathlon-fx|Xathlon64-sse3|Xk8-sse3|Xopteron-sse3) ;; X) if test x$with_cpu_64 = x; then @@ -1427,7 +1427,7 @@ ;; *) echo "Unsupported CPU used in --with-cpu=$with_cpu, supported values:" 1>&2 - echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 + echo "generic atom core2 corei7 Xcorei7-avx nocona x86-64 bdver3 bdver2 bdver1 btver2 btver1 amdfam10 barcelona k8 opteron athlon64 athlon-fx athlon64-sse3 k8-sse3 opteron-sse3" 1>&2 exit 1 ;; esac @@ -2660,6 +2660,10 @@ ;; i686-*-* | i786-*-*) case ${target_noncanonical} in + bdver3-*) + arch=bdver3 + cpu=bdver3 + ;; bdver2-*) arch=bdver2 cpu=bdver2 @@ -2761,6 +2765,10 @@ ;; x86_64-*-*) case ${target_noncanonical} in + bdver3-*) + arch=bdver3 + cpu=bdver3 + ;; bdver2-*) arch=bdver2 cpu=bdver2 @@ -3211,8 +3219,8 @@ ;; "" | x86-64 | generic | native \ | k8 | k8-sse3 | athlon64 | athlon64-sse3 | opteron \ - | opteron-sse3 | athlon-fx | bdver2 | bdver1 | btver2 | btver1 \ - | amdfam10 | barcelona | nocona | core2 | corei7 \ + | opteron-sse3 | athlon-fx | bdver3 | bdver2 | bdver1 | btver2 \ + | btver1 | amdfam10 | barcelona | nocona | core2 | corei7 \ | corei7-avx | core-avx-i | core-avx2 | atom) # OK ;; Index: gcc/config/i386/i386.h =================================================================== --- gcc/config/i386/i386.h (revision 192031) +++ gcc/config/i386/i386.h (working copy) @@ -251,6 +251,7 @@ #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) +#define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) @@ -610,6 +611,7 @@ TARGET_CPU_DEFAULT_amdfam10, TARGET_CPU_DEFAULT_bdver1, TARGET_CPU_DEFAULT_bdver2, + TARGET_CPU_DEFAULT_bdver3, TARGET_CPU_DEFAULT_btver1, TARGET_CPU_DEFAULT_btver2, @@ -2092,6 +2094,7 @@ PROCESSOR_AMDFAM10, PROCESSOR_BDVER1, PROCESSOR_BDVER2, + PROCESSOR_BDVER3, PROCESSOR_BTVER1, PROCESSOR_BTVER2, PROCESSOR_ATOM, Index: gcc/config/i386/i386.md =================================================================== --- gcc/config/i386/i386.md (revision 192031) +++ gcc/config/i386/i386.md (working copy) @@ -313,7 +313,7 @@ ;; Processor type. (define_attr "cpu" "none,pentium,pentiumpro,geode,k6,athlon,k8,core2,corei7, - atom,generic64,amdfam10,bdver1,bdver2,btver1,btver2" + atom,generic64,amdfam10,bdver1,bdver2,bdver3,btver1,btver2" (const (symbol_ref "ix86_schedule"))) ;; A basic instruction type. Refinements due to arguments to be @@ -326,7 +326,7 @@ push,pop,call,callv,leave, str,bitmanip, fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint, - sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul, + sselog,sselog1,sseiadd,sseiadd1,sseishft,sseishft1,sseimul,sseshuf, sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,ssecvt1,sseicvt,ssediv,sseins, ssemuladd,sse4arg,lwp, mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft" @@ -937,6 +937,7 @@ (include "k6.md") (include "athlon.md") (include "bdver1.md") +(include "bdver3.md") (include "geode.md") (include "atom.md") (include "core2.md") Index: gcc/config/i386/cpuid.h =================================================================== --- gcc/config/i386/cpuid.h (revision 192031) +++ gcc/config/i386/cpuid.h (working copy) @@ -75,6 +75,9 @@ #define bit_RDSEED (1 << 18) #define bit_ADX (1 << 19) +/* Extended Features with cpuid function 0xd */ +#define bit_XSAVEOPT (1 << 0) + /* Signatures for different CPU implementations as returned in uses of cpuid with level 0. */ #define signature_AMD_ebx 0x68747541 Index: gcc/config/i386/sse.md =================================================================== --- gcc/config/i386/sse.md (revision 192031) +++ gcc/config/i386/sse.md (working copy) @@ -3711,7 +3711,10 @@ return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}"; } - [(set_attr "type" "sselog") + [(set (attr "type") + (if_then_else (eq_attr "cpu" "bdver3") + (const_string "sseshuf") + (const_string "sselog"))) (set_attr "length_immediate" "1") (set_attr "prefix" "vex") (set_attr "mode" "V8SF")]) @@ -3762,7 +3765,10 @@ } } [(set_attr "isa" "noavx,avx") - (set_attr "type" "sselog") + (set (attr "type") + (if_then_else (eq_attr "cpu" "bdver3") + (const_string "sseshuf") + (const_string "sselog"))) (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex") (set_attr "mode" "V4SF")]) @@ -3869,7 +3875,27 @@ vmovlps\t{%2, %1, %0|%0, %1, %2} %vmovlps\t{%2, %0|%0, %2}" [(set_attr "isa" "noavx,avx,noavx,avx,*") - (set_attr "type" "sselog,sselog,ssemov,ssemov,ssemov") + (set (attr "type") + (cond [(and (eq_attr "cpu" "bdver3") + (eq_attr "alternative" "0")) + (const_string "sseshuf") + (and (eq_attr "cpu" "bdver3") + (eq_attr "alternative" "1")) + (const_string "sseshuf") + (eq_attr "alternative" "2") + (const_string "ssemov") + (eq_attr "alternative" "3") + (const_string "ssemov") + (eq_attr "alternative" "4") + (const_string "ssemov") + (and (not (eq_attr "cpu" "bdver3")) + (eq_attr "alternative" "0")) + (const_string "sselog") + (and (not (eq_attr "cpu" "bdver3")) + (eq_attr "alternative" "1")) + (const_string "sselog") + ] + (const_string "*" ))) (set_attr "length_immediate" "1,1,*,*,*") (set_attr "prefix" "orig,vex,orig,vex,maybe_vex") (set_attr "mode" "V4SF,V4SF,V2SF,V2SF,V2SF")]) @@ -3923,7 +3949,23 @@ vbroadcastss\t{%1, %0|%0, %1} shufps\t{$0, %0, %0|%0, %0, 0}" [(set_attr "isa" "avx,avx,noavx") - (set_attr "type" "sselog1,ssemov,sselog1") + (set (attr "type") + (cond [(and (eq_attr "cpu" "bdver3") + (eq_attr "alternative" "0")) + (const_string "sseshuf") + (and (eq_attr "cpu" "bdver3") + (eq_attr "alternative" "2")) + (const_string "sseshuf") + (eq_attr "alternative" "1") + (const_string "ssemov") + (and (not (eq_attr "cpu" "bdver3")) + (eq_attr "alternative" "0")) + (const_string "sselog1") + (and (not (eq_attr "cpu" "bdver3")) + (eq_attr "alternative" "2")) + (const_string "sselog1") + ] + (const_string "*" ))) (set_attr "length_immediate" "1,0,1") (set_attr "prefix_extra" "0,1,*") (set_attr "prefix" "vex,vex,orig") @@ -4653,7 +4695,10 @@ return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"; } - [(set_attr "type" "sselog") + [(set (attr "type") + (if_then_else (eq_attr "cpu" "bdver3") + (const_string "sseshuf") + (const_string "sselog"))) (set_attr "length_immediate" "1") (set_attr "prefix" "vex") (set_attr "mode" "V4DF")]) @@ -4767,7 +4812,10 @@ } } [(set_attr "isa" "noavx,avx") - (set_attr "type" "sselog") + (set (attr "type") + (if_then_else (eq_attr "cpu" "bdver3") + (const_string "sseshuf") + (const_string "sselog"))) (set_attr "length_immediate" "1") (set_attr "prefix" "orig,vex") (set_attr "mode" "V2DF")]) Index: gcc/config/i386/i386.opt =================================================================== --- gcc/config/i386/i386.opt (revision 192031) +++ gcc/config/i386/i386.opt (working copy) @@ -419,7 +419,7 @@ mdispatch-scheduler Target RejectNegative Var(flag_dispatch_scheduler) -Do dispatch scheduling if processor is bdver1 or bdver2 and Haifa scheduling +Do dispatch scheduling if processor is bdver1 or bdver2 or bdver3 and Haifa scheduling is selected. mprefer-avx128 Index: gcc/config/i386/i386-c.c =================================================================== --- gcc/config/i386/i386-c.c (revision 192031) +++ gcc/config/i386/i386-c.c (working copy) @@ -114,6 +114,10 @@ def_or_undef (parse_in, "__bdver2"); def_or_undef (parse_in, "__bdver2__"); break; + case PROCESSOR_BDVER3: + def_or_undef (parse_in, "__bdver3"); + def_or_undef (parse_in, "__bdver3__"); + break; case PROCESSOR_BTVER1: def_or_undef (parse_in, "__btver1"); def_or_undef (parse_in, "__btver1__"); @@ -209,7 +213,10 @@ case PROCESSOR_BDVER2: def_or_undef (parse_in, "__tune_bdver2__"); break; - case PROCESSOR_BTVER1: + case PROCESSOR_BDVER3: + def_or_undef (parse_in, "__tune_bdver3__"); + break; + case PROCESSOR_BTVER1: def_or_undef (parse_in, "__tune_btver1__"); break; case PROCESSOR_BTVER2: Index: gcc/config/i386/driver-i386.c =================================================================== --- gcc/config/i386/driver-i386.c (revision 192031) +++ gcc/config/i386/driver-i386.c (working copy) @@ -391,6 +391,7 @@ unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0; unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0; unsigned int has_osxsave = 0; + unsigned int has_xsaveopt = 0; bool arch; @@ -460,6 +461,12 @@ has_fsgsbase = ebx & bit_FSGSBASE; has_rdseed = ebx & bit_RDSEED; has_adx = ebx & bit_ADX; + + /* call the extended function dh with ecx=1 + to get the cpuid flag value of xsaveopt */ + __cpuid_count (0xd, 1, eax, ebx, ecx,edx); + + has_xsaveopt = eax & bit_XSAVEOPT ; } /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ @@ -530,6 +537,8 @@ processor = PROCESSOR_GEODE; else if (has_movbe) processor = PROCESSOR_BTVER2; + else if (has_xsaveopt) + processor = PROCESSOR_BDVER3; else if (has_bmi) processor = PROCESSOR_BDVER2; else if (has_xop) @@ -700,6 +709,9 @@ case PROCESSOR_BDVER2: cpu = "bdver2"; break; + case PROCESSOR_BDVER3: + cpu = "bdver3"; + break; case PROCESSOR_BTVER1: cpu = "btver1"; break; Index: gcc/config/i386/i386.c =================================================================== --- gcc/config/i386/i386.c (revision 192031) +++ gcc/config/i386/i386.c (working copy) @@ -1427,6 +1427,85 @@ 1, /* cond_not_taken_branch_cost. */ }; +struct processor_costs bdver3_cost = { + COSTS_N_INSNS (1), /* cost of an add instruction */ + COSTS_N_INSNS (1), /* cost of a lea instruction */ + COSTS_N_INSNS (1), /* variable shift costs */ + COSTS_N_INSNS (1), /* constant shift costs */ + {COSTS_N_INSNS (4), /* cost of starting multiply for QI */ + COSTS_N_INSNS (4), /* HI */ + COSTS_N_INSNS (4), /* SI */ + COSTS_N_INSNS (6), /* DI */ + COSTS_N_INSNS (6)}, /* other */ + 0, /* cost of multiply per each bit set */ + {COSTS_N_INSNS (19), /* cost of a divide/mod for QI */ + COSTS_N_INSNS (35), /* HI */ + COSTS_N_INSNS (51), /* SI */ + COSTS_N_INSNS (83), /* DI */ + COSTS_N_INSNS (83)}, /* other */ + COSTS_N_INSNS (1), /* cost of movsx */ + COSTS_N_INSNS (1), /* cost of movzx */ + 8, /* "large" insn */ + 9, /* MOVE_RATIO */ + 4, /* cost for loading QImode using movzbl */ + {5, 5, 4}, /* cost of loading integer registers + in QImode, HImode and SImode. + Relative to reg-reg move (2). */ + {4, 4, 4}, /* cost of storing integer registers */ + 2, /* cost of reg,reg fld/fst */ + {5, 5, 12}, /* cost of loading fp registers + in SFmode, DFmode and XFmode */ + {4, 4, 8}, /* cost of storing fp registers + in SFmode, DFmode and XFmode */ + 2, /* cost of moving MMX register */ + {4, 4}, /* cost of loading MMX registers + in SImode and DImode */ + {4, 4}, /* cost of storing MMX registers + in SImode and DImode */ + 2, /* cost of moving SSE register */ + {4, 4, 4}, /* cost of loading SSE registers + in SImode, DImode and TImode */ + {4, 4, 4}, /* cost of storing SSE registers + in SImode, DImode and TImode */ + 2, /* MMX or SSE register to integer */ + 16, /* size of l1 cache. */ + 2048, /* size of l2 cache. */ + 64, /* size of prefetch block */ + /* New AMD processors never drop prefetches; if they cannot be performed + immediately, they are queued. We set number of simultaneous prefetches + to a large constant to reflect this (it probably is not a good idea not + to limit number of prefetches at all, as their execution also takes some + time). */ + 100, /* number of parallel prefetches */ + 2, /* Branch cost */ + COSTS_N_INSNS (6), /* cost of FADD and FSUB insns. */ + COSTS_N_INSNS (6), /* cost of FMUL instruction. */ + COSTS_N_INSNS (42), /* cost of FDIV instruction. */ + COSTS_N_INSNS (2), /* cost of FABS instruction. */ + COSTS_N_INSNS (2), /* cost of FCHS instruction. */ + COSTS_N_INSNS (52), /* cost of FSQRT instruction. */ + + /* BDVER3 has optimized REP instruction for medium sized blocks, but for + very small blocks it is better to use loop. For large blocks, libcall + can do nontemporary accesses and beat inline considerably. */ + {{libcall, {{6, loop}, {14, unrolled_loop}, {-1, rep_prefix_4_byte}}}, + {libcall, {{16, loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}, + {{libcall, {{8, loop}, {24, unrolled_loop}, + {2048, rep_prefix_4_byte}, {-1, libcall}}}, + {libcall, {{48, unrolled_loop}, {8192, rep_prefix_8_byte}, {-1, libcall}}}}, + 6, /* scalar_stmt_cost. */ + 4, /* scalar load_cost. */ + 4, /* scalar_store_cost. */ + 6, /* vec_stmt_cost. */ + 0, /* vec_to_scalar_cost. */ + 2, /* scalar_to_vec_cost. */ + 4, /* vec_align_load_cost. */ + 4, /* vec_unalign_load_cost. */ + 4, /* vec_store_cost. */ + 2, /* cond_taken_branch_cost. */ + 1, /* cond_not_taken_branch_cost. */ +}; + struct processor_costs btver1_cost = { COSTS_N_INSNS (1), /* cost of an add instruction */ COSTS_N_INSNS (2), /* cost of a lea instruction */ @@ -1987,7 +2066,8 @@ #define m_AMDFAM10 (1<