From patchwork Wed Oct 10 23:12:57 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 190808 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id D7B682C0084 for ; Thu, 11 Oct 2012 17:01:38 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 4BE244A164; Thu, 11 Oct 2012 08:01:37 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id PPVO-Hjz6TuL; Thu, 11 Oct 2012 08:01:37 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3204E4A17F; Thu, 11 Oct 2012 08:01:35 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 486794A17B for ; Thu, 11 Oct 2012 08:01:33 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id dB4eTr65lR+X for ; Thu, 11 Oct 2012 08:01:32 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yh0-f74.google.com (mail-yh0-f74.google.com [209.85.213.74]) by theia.denx.de (Postfix) with ESMTPS id DA8414A194 for ; Thu, 11 Oct 2012 08:01:15 +0200 (CEST) Received: by mail-yh0-f74.google.com with SMTP id 10so166188yhl.3 for ; Wed, 10 Oct 2012 23:01:14 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=B7zRW7byFoOYkmfzMnlYJGSAgmmwpbuxSKTdKQkePBo=; b=TkJA+3V/8mbNWGOOGxFdlXOQMS3eN8Hn0wTRHHrn748Cy5eYugWBd7AsbUztWxeyzi R3IWaONsig3OOGVj277PCjawNXrN5NcoX1WybC+lePGfvx5AjL0BdyVwzKiuh+xCkyUP QovuNZxQpWN5R4LM6wt24BnG6FDD8fHDgShVDoyrenhJ2m8QYgkKno6pRttgYYs4sB6k p5Q9Qt6iq7hlCmEgVMFAfWReciFokgxV2Vt2I2DIk++NC6VT6Xyq7JZhCypG89bLnr+A w/4LEWCVm0e3Zmz2E1XcttxN3JEVPogSropdhX1P63g5eMF94jHD9MBW8AUiy9KZowMT 8DAg== Received: by 10.236.123.43 with SMTP id u31mr15076261yhh.43.1349910813191; Wed, 10 Oct 2012 16:13:33 -0700 (PDT) Received: from wpzn4.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id i7si264629yhj.6.2012.10.10.16.13.33 (version=TLSv1/SSLv3 cipher=AES128-SHA); Wed, 10 Oct 2012 16:13:33 -0700 (PDT) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by wpzn4.hot.corp.google.com (Postfix) with ESMTP id 19CDF1E0043; Wed, 10 Oct 2012 16:13:33 -0700 (PDT) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id B17201643B3; Wed, 10 Oct 2012 16:13:32 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 10 Oct 2012 16:12:57 -0700 Message-Id: <1349910781-32088-7-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1349910781-32088-1-git-send-email-sjg@chromium.org> References: <1349910781-32088-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQmUQVTNH8Z/2NnFB9h/v8b6xtRqo6GdWQguvKZRqtdA9bG0IBv0z+LUfa1UdBf/kR1GaEadGmoBRYs7r4txDDhnmohXI3H/5xkswynOCmV2eYi5dOZoOyN15Ro7CZAlBGyB2c+mTEaoe0qc41lGMMTnai7V4A/+a711CmhV5+zBY21gFRA2lC3Oo18lqB5lqEyrOm+W Cc: Vadim Bendebury , Stefan Reinauer Subject: [U-Boot] [PATCH v2 06/10] x86: coreboot: Tell u-boot about PCI bus 0 when initializing X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Gabe Black U-boot needs a host controller or "hose" to interact with the PCI busses behind them. This change installs a host controller during initialization of the coreboot "board" which implements some of X86's basic PCI semantics. This relies on some existing generic code, but also duplicates a little bit of code from the sc520 implementation. Ideally we'd eliminate that duplication at some point. It looks like in order to scan buses beyond bus 0, we'll need to tell u-boot's generic PCI configuration code what to do if it encounters a bridge, specifically to scan the bus on the other side of it. Signed-off-by: Gabe Black Signed-off-by: Simon Glass Acked-by: Graeme Russ --- arch/x86/cpu/coreboot/pci.c | 15 +++++++++++++++ arch/x86/include/asm/pci.h | 2 +- 2 files changed, 16 insertions(+), 1 deletions(-) diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 732ca3c..0ddc975 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -25,6 +25,21 @@ * MA 02111-1307 USA */ +#include +#include +#include + +static struct pci_controller coreboot_hose; + void pci_init_board(void) { + coreboot_hose.first_busno = 0; + coreboot_hose.last_busno = 0xff; + coreboot_hose.region_count = 0; + + pci_setup_type1(&coreboot_hose); + + pci_register_hose(&coreboot_hose); + + coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose); } diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h index 37cc7e3..6d68ab6 100644 --- a/arch/x86/include/asm/pci.h +++ b/arch/x86/include/asm/pci.h @@ -24,7 +24,7 @@ */ #ifndef _PCI_I386_H_ -#define _PCI_I386_H_ 1 +#define _PCI_I386_H_ #define DEFINE_PCI_DEVICE_TABLE(_table) \ const struct pci_device_id _table[]