From patchwork Thu Oct 11 03:58:54 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabio Estevam X-Patchwork-Id: 190796 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 49F6C2C008C for ; Thu, 11 Oct 2012 16:39:02 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 25D1A4A044; Thu, 11 Oct 2012 07:38:59 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 0plaFZM3CJWd; Thu, 11 Oct 2012 07:38:58 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 1FC094A03C; Thu, 11 Oct 2012 07:38:58 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 7D6B64A03C for ; Thu, 11 Oct 2012 07:38:56 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VlUiIll1mRMr for ; Thu, 11 Oct 2012 07:38:45 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-yh0-f44.google.com (mail-yh0-f44.google.com [209.85.213.44]) by theia.denx.de (Postfix) with ESMTPS id 6519E4A03B for ; Thu, 11 Oct 2012 07:38:44 +0200 (CEST) Received: by mail-yh0-f44.google.com with SMTP id 56so384289yhq.3 for ; Wed, 10 Oct 2012 22:38:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references; bh=vwqrprR0w0VoY1z42I3C431O2X48M27B7+6NZJADFMA=; b=hIKF7q0L2BdL9+4jviIzk2IZiq7Ugsgvxkm/bFWqHahYCHjy4qkalztLO5T1gVV3Wx Y8EygwlPFCS/N1QPqkjIkh4jGDFbWj4QQqQY4gcdZU+U9gQ1LFcA9QkO8jPhUA+0ALSc V0OsDggHfH/7VgA/yL+8xsD6mGih5CsT7mn+p2ddU/OieXe2xSJmMQJb+fteexaqGREb a0LCgt+x2mAhg55DRxEL5YggO0wj8ZNHhjd15dujL9MPJ1qvWiN4KwKABmafcbazI4xj eVMm6oNZ+Ch9ZYnVoA+Nvw8n4TmOBurK4dm/1E8yltK01YsFVoRMJd8b6uYXDV8ZmQP3 +YKQ== Received: by 10.100.78.6 with SMTP id a6mr5358094anb.80.1349927972013; Wed, 10 Oct 2012 20:59:32 -0700 (PDT) Received: from fabio-Latitude-E6410.cps.virtua.com.br ([201.82.136.72]) by mx.google.com with ESMTPS id m13sm2909507ank.16.2012.10.10.20.59.29 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 10 Oct 2012 20:59:31 -0700 (PDT) From: Fabio Estevam To: sbabic@denx.de Date: Thu, 11 Oct 2012 00:58:54 -0300 Message-Id: <1349927934-3063-3-git-send-email-festevam@gmail.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349927934-3063-1-git-send-email-festevam@gmail.com> References: <1349927934-3063-1-git-send-email-festevam@gmail.com> Cc: Fabio Estevam , u-boot@lists.denx.de Subject: [U-Boot] [PATCH 3/3] mx25pdk: Add FEC support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Fabio Estevam mx25pdk has a Ethernet port that is connected to its internal FEC controller. In order to power up the Ethernet PHY (DP83640) it is necessary to communicate with the PMIC via I2C. Make FEC ethernet functional. Signed-off-by: Fabio Estevam --- board/freescale/mx25pdk/mx25pdk.c | 64 +++++++++++++++++++++++++++++++++++++ include/configs/mx25pdk.h | 15 +++++++++ 2 files changed, 79 insertions(+) diff --git a/board/freescale/mx25pdk/mx25pdk.c b/board/freescale/mx25pdk/mx25pdk.c index e850b3e..e1fa2be 100644 --- a/board/freescale/mx25pdk/mx25pdk.c +++ b/board/freescale/mx25pdk/mx25pdk.c @@ -25,6 +25,13 @@ #include #include #include +#include + +#define FEC_RESET_B IMX_GPIO_NR(2, 3) +#define FEC_ENABLE_B IMX_GPIO_NR(4, 8) +#define CARD_DETECT IMX_GPIO_NR(2, 1) +#define PMIC_I2C_ADDR 0x54 +#define REG_PHY_3V3 0x02 #define CARD_DETECT IMX_GPIO_NR(2, 1) @@ -36,6 +43,47 @@ struct fsl_esdhc_cfg esdhc_cfg[1] = { }; #endif +static void mx25pdk_fec_init(void) +{ + struct iomuxc_mux_ctl *muxctl; + struct iomuxc_pad_ctl *padctl; + u32 gpio_mux_mode = MX25_PIN_MUX_MODE(5); + u32 gpio_mux_mode0_sion = MX25_PIN_MUX_MODE(0) | MX25_PIN_MUX_SION; + + /* FEC pin init is generic */ + mx25_fec_init_pins(); + + muxctl = (struct iomuxc_mux_ctl *)IMX_IOPADMUX_BASE; + padctl = (struct iomuxc_pad_ctl *)IMX_IOPADCTL_BASE; + /* + * Set up FEC_RESET_B and FEC_ENABLE_B + * + * FEC_RESET_B: gpio2_3 is ALT 5 mode of pin D12 + * FEC_ENABLE_B: gpio4_8 is ALT 5 mode of pin A17 + */ + writel(gpio_mux_mode, &muxctl->pad_d12); + writel(gpio_mux_mode, &muxctl->pad_a17); + + writel(0x0, &padctl->pad_d12); + writel(0x0, &padctl->pad_a17); + + /* Assert RESET and ENABLE low */ + gpio_direction_output(FEC_RESET_B, 0); + gpio_direction_output(FEC_ENABLE_B, 0); + + udelay(10); + + /* Deassert RESET and ENABLE */ + gpio_set_value(FEC_RESET_B, 1); + gpio_set_value(FEC_ENABLE_B, 1); + + /* Setup I2C pins so that PMIC can turn on PHY supply */ + writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_clk); + writel(gpio_mux_mode0_sion, &muxctl->pad_i2c1_dat); + writel(0x1E8, &padctl->pad_i2c1_clk); + writel(0x1E8, &padctl->pad_i2c1_dat); +} + int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ @@ -59,6 +107,22 @@ int board_init(void) return 0; } +int board_late_init(void) +{ + /* Turn on PHY supply via I2C command to PMIC */ + u8 reg[4]; + reg[0] = 0x09; + + mx25pdk_fec_init(); + + if (i2c_write(PMIC_I2C_ADDR, REG_PHY_3V3, 1, reg, 1)) { + printf("I2C write to PMIC failed\n"); + return -EINVAL; + } + + return 0; +} + #ifdef CONFIG_FSL_ESDHC int board_mmc_getcd(struct mmc *mmc) { diff --git a/include/configs/mx25pdk.h b/include/configs/mx25pdk.h index 1770521..9b010c2 100644 --- a/include/configs/mx25pdk.h +++ b/include/configs/mx25pdk.h @@ -41,6 +41,7 @@ #define PHYS_SDRAM_1_SIZE (64 * 1024 * 1024) #define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ @@ -100,6 +101,20 @@ #define CONFIG_DOS_PARTITION +/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_BASE IMX_I2C_BASE +#define CONFIG_SYS_I2C_SPEED 100000 + +/* Ethernet Configs */ + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET + #define CONFIG_BOOTDELAY 3 #define CONFIG_LOADADDR 0x81000000 /* loadaddr env var */