From patchwork Tue Oct 9 20:27:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 190463 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id BD4E22C00A6 for ; Wed, 10 Oct 2012 08:33:42 +1100 (EST) Received: from localhost ([::1]:45937 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgPq-0000il-DA for incoming@patchwork.ozlabs.org; Tue, 09 Oct 2012 16:28:34 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48179) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP6-0007NA-7h for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLgP1-0004OG-Uf for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:48 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45235) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP1-0004Nc-Ok for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:43 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TLgP0-0006xp-P5; Tue, 09 Oct 2012 22:27:42 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TLgOy-0005g7-CQ; Tue, 09 Oct 2012 22:27:40 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2012 22:27:30 +0200 Message-Id: <1349814458-21739-7-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> References: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 06/14] target-mips: optimize load operations X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Only allocate t1 when needed. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target-mips/translate.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c1438ff..f7d9467 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1135,7 +1135,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } t0 = tcg_temp_new(); - t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, base, offset); switch (opc) { @@ -1160,22 +1159,27 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_LDL: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "ldl"; break; case OPC_LDR: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "ldr"; break; case OPC_LDPC: save_cpu_state(ctx, 0); - tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); + t1 = tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); + tcg_temp_free(t1); tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "ldpc"; @@ -1183,8 +1187,9 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, #endif case OPC_LWPC: save_cpu_state(ctx, 0); - tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); + t1 = tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); + tcg_temp_free(t1); tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lwpc"; @@ -1221,16 +1226,20 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_LWL: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "lwl"; break; case OPC_LWR: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "lwr"; break; case OPC_LL: @@ -1243,7 +1252,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t0); - tcg_temp_free(t1); } /* Store */