Patchwork [06/14] target-mips: optimize load operations

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Submitter Aurelien Jarno
Date Oct. 9, 2012, 8:27 p.m.
Message ID <1349814458-21739-7-git-send-email-aurelien@aurel32.net>
Download mbox | patch
Permalink /patch/190463/
State New
Headers show

Comments

Aurelien Jarno - Oct. 9, 2012, 8:27 p.m.
Only allocate t1 when needed.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-mips/translate.c |   16 ++++++++++++----
 1 file changed, 12 insertions(+), 4 deletions(-)
Richard Henderson - Oct. 10, 2012, 8:11 p.m.
On 10/09/2012 01:27 PM, Aurelien Jarno wrote:
> Only allocate t1 when needed.
> 
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

Reviewed-by: Richard Henderson <rth@twiddle.net>


r~

Patch

diff --git a/target-mips/translate.c b/target-mips/translate.c
index c1438ff..f7d9467 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1135,7 +1135,6 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
     }
 
     t0 = tcg_temp_new();
-    t1 = tcg_temp_new();
     gen_base_offset_addr(ctx, t0, base, offset);
 
     switch (opc) {
@@ -1160,22 +1159,27 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
         break;
     case OPC_LDL:
         save_cpu_state(ctx, 1);
+        t1 = tcg_temp_new();
         gen_load_gpr(t1, rt);
         gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
+        tcg_temp_free(t1);
         opn = "ldl";
         break;
     case OPC_LDR:
         save_cpu_state(ctx, 1);
+        t1 = tcg_temp_new();
         gen_load_gpr(t1, rt);
         gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
+        tcg_temp_free(t1);
         opn = "ldr";
         break;
     case OPC_LDPC:
         save_cpu_state(ctx, 0);
-        tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
+        t1 = tcg_const_tl(pc_relative_pc(ctx));
         gen_op_addr_add(ctx, t0, t0, t1);
+        tcg_temp_free(t1);
         tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx);
         gen_store_gpr(t0, rt);
         opn = "ldpc";
@@ -1183,8 +1187,9 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
 #endif
     case OPC_LWPC:
         save_cpu_state(ctx, 0);
-        tcg_gen_movi_tl(t1, pc_relative_pc(ctx));
+        t1 = tcg_const_tl(pc_relative_pc(ctx));
         gen_op_addr_add(ctx, t0, t0, t1);
+        tcg_temp_free(t1);
         tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx);
         gen_store_gpr(t0, rt);
         opn = "lwpc";
@@ -1221,16 +1226,20 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
         break;
     case OPC_LWL:
         save_cpu_state(ctx, 1);
+        t1 = tcg_temp_new();
         gen_load_gpr(t1, rt);
         gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
+        tcg_temp_free(t1);
         opn = "lwl";
         break;
     case OPC_LWR:
         save_cpu_state(ctx, 1);
+        t1 = tcg_temp_new();
         gen_load_gpr(t1, rt);
         gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx);
         gen_store_gpr(t1, rt);
+        tcg_temp_free(t1);
         opn = "lwr";
         break;
     case OPC_LL:
@@ -1243,7 +1252,6 @@  static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
     (void)opn; /* avoid a compiler warning */
     MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]);
     tcg_temp_free(t0);
-    tcg_temp_free(t1);
 }
 
 /* Store */