From patchwork Tue Oct 9 20:27:36 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 190461 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 542862C0091 for ; Wed, 10 Oct 2012 08:28:55 +1100 (EST) Received: from localhost ([::1]:47087 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgQB-0001L2-UJ for incoming@patchwork.ozlabs.org; Tue, 09 Oct 2012 16:28:55 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48211) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP7-0007NO-D5 for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLgP2-0004PF-Nw for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:49 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45244) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP2-0004Os-IX for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:44 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TLgP1-0006xu-4O; Tue, 09 Oct 2012 22:27:43 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TLgOy-0005gb-L0; Tue, 09 Oct 2012 22:27:40 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2012 22:27:36 +0200 Message-Id: <1349814458-21739-13-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> References: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 12/14] target-mips: use deposit instead of hardcoded version X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use the deposit op instead of and hardcoded bit field insertion. It allows the host to emit the corresponding instruction if available. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target-mips/translate.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 7d87f66..d996fd2 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -3406,7 +3406,6 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); - target_ulong mask; gen_load_gpr(t1, rs); switch (opc) { @@ -3439,45 +3438,27 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, case OPC_INS: if (lsb > msb) goto fail; - mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) << lsb; gen_load_gpr(t0, rt); - tcg_gen_andi_tl(t0, t0, ~mask); - tcg_gen_shli_tl(t1, t1, lsb); - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); tcg_gen_ext32s_tl(t0, t0); break; #if defined(TARGET_MIPS64) case OPC_DINSM: if (lsb > msb) goto fail; - mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) - 1) : ~0ULL) << lsb; - gen_load_gpr(t0, rt); - tcg_gen_andi_tl(t0, t0, ~mask); - tcg_gen_shli_tl(t1, t1, lsb); - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1); break; case OPC_DINSU: if (lsb > msb) goto fail; - mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32); gen_load_gpr(t0, rt); - tcg_gen_andi_tl(t0, t0, ~mask); - tcg_gen_shli_tl(t1, t1, lsb + 32); - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1); break; case OPC_DINS: if (lsb > msb) goto fail; gen_load_gpr(t0, rt); - mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb; - gen_load_gpr(t0, rt); - tcg_gen_andi_tl(t0, t0, ~mask); - tcg_gen_shli_tl(t1, t1, lsb); - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); break; #endif default: