From patchwork Tue Oct 9 20:27:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 190452 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 830DA2C0094 for ; Wed, 10 Oct 2012 08:15:35 +1100 (EST) Received: from localhost ([::1]:45933 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgPk-0000if-Qz for incoming@patchwork.ozlabs.org; Tue, 09 Oct 2012 16:28:28 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48140) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP5-0007Mt-F1 for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLgP2-0004P9-OW for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:47 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45239) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP2-0004Ok-Gd for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:44 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TLgP1-0006xr-1B; Tue, 09 Oct 2012 22:27:43 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TLgOy-0005gM-GQ; Tue, 09 Oct 2012 22:27:40 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2012 22:27:33 +0200 Message-Id: <1349814458-21739-10-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> References: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 09/14] target-mips: don't use local temps for store conditional X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Store conditional operations only need local temps in user mode. Fix the code to use temp local only in user mode, this spares two memory stores in system mode. At the same time remove a wrong a wrong copied & pasted comment, store operations don't have a register destination. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target-mips/translate.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 8a7462b..b6eb46a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1375,13 +1375,14 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, const char *opn = "st_cond"; TCGv t0, t1; +#ifdef CONFIG_USER_ONLY t0 = tcg_temp_local_new(); - - gen_base_offset_addr(ctx, t0, base, offset); - /* Don't do NOP if destination is zero: we must perform the actual - memory access. */ - t1 = tcg_temp_local_new(); +#else + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); +#endif + gen_base_offset_addr(ctx, t0, base, offset); gen_load_gpr(t1, rt); switch (opc) { #if defined(TARGET_MIPS64)