From patchwork Tue Oct 9 20:27:28 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 190450 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 18FA42C009F for ; Wed, 10 Oct 2012 08:08:54 +1100 (EST) Received: from localhost ([::1]:46477 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgPx-000115-Kk for incoming@patchwork.ozlabs.org; Tue, 09 Oct 2012 16:28:41 -0400 Received: from eggs.gnu.org ([208.118.235.92]:48156) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP5-0007N1-RB for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLgP1-0004OA-Ua for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:47 -0400 Received: from hall.aurel32.net ([88.191.126.93]:45234) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgP1-0004NQ-IS for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:27:43 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TLgP0-0006xn-4X; Tue, 09 Oct 2012 22:27:42 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TLgOy-0005fx-9b; Tue, 09 Oct 2012 22:27:40 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2012 22:27:28 +0200 Message-Id: <1349814458-21739-5-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> References: <1349814458-21739-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Aurelien Jarno Subject: [Qemu-devel] [PATCH 04/14] target-mips: use softfloat constants when possible X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org softfloat already has a few constants defined, use them instead of redefining them in target-mips. Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and FP_TO_INT64_OVERFLOW as even if they have the same value, they are technically different (and defined differently in the MIPS ISA). Remove the unused constants. Signed-off-by: Aurelien Jarno Reviewed-by: Richard Henderson --- target-mips/op_helper.c | 157 +++++++++++++++++++++++++++-------------------- 1 file changed, 89 insertions(+), 68 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index bd3c37c..647858d 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2317,14 +2317,10 @@ void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr, /* Complex FPU operations which may need stack space. */ -#define FLOAT_ONE32 make_float32(0x3f8 << 20) -#define FLOAT_ONE64 make_float64(0x3ffULL << 52) #define FLOAT_TWO32 make_float32(1 << 30) #define FLOAT_TWO64 make_float64(1ULL << 62) -#define FLOAT_QNAN32 0x7fbfffff -#define FLOAT_QNAN64 0x7ff7ffffffffffffULL -#define FLOAT_SNAN32 0x7fffffff -#define FLOAT_SNAN64 0x7fffffffffffffffULL +#define FP_TO_INT32_OVERFLOW 0x7fffffff +#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL /* convert MIPS rounding mode in FCR31 to IEEE library */ static unsigned int ieee_rm[] = { @@ -2495,8 +2491,9 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2507,8 +2504,9 @@ uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2534,14 +2532,14 @@ uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); excp = get_float_exception_flags(&env->active_fpu.fp_status); if (excp & (float_flag_overflow | float_flag_invalid)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } set_float_exception_flags(0, &env->active_fpu.fp_status); wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); excph = get_float_exception_flags(&env->active_fpu.fp_status); if (excph & (float_flag_overflow | float_flag_invalid)) { - wth2 = FLOAT_SNAN32; + wth2 = FP_TO_INT32_OVERFLOW; } set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); @@ -2607,8 +2605,9 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2619,8 +2618,9 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2633,8 +2633,9 @@ uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2647,8 +2648,9 @@ uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2661,8 +2663,9 @@ uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2675,8 +2678,9 @@ uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2687,8 +2691,9 @@ uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2699,8 +2704,9 @@ uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2711,8 +2717,9 @@ uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2723,8 +2730,9 @@ uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2737,8 +2745,9 @@ uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2751,8 +2760,9 @@ uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2765,8 +2775,9 @@ uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2779,8 +2790,9 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2793,8 +2805,9 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2807,8 +2820,9 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - dt2 = FLOAT_SNAN64; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + dt2 = FP_TO_INT64_OVERFLOW; + } return dt2; } @@ -2821,8 +2835,9 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2835,8 +2850,9 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) - wt2 = FLOAT_SNAN32; + if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + wt2 = FP_TO_INT32_OVERFLOW; + } return wt2; } @@ -2869,7 +2885,7 @@ uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); - fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); + fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; } @@ -2879,7 +2895,7 @@ uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; } @@ -2890,7 +2906,7 @@ uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); - fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); + fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; } @@ -2901,7 +2917,7 @@ uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); update_fcr31(env); return fst2; } @@ -2911,7 +2927,7 @@ uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) uint64_t fdt2; set_float_exception_flags(0, &env->active_fpu.fp_status); - fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); + fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; } @@ -2921,7 +2937,7 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) uint32_t fst2; set_float_exception_flags(0, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; } @@ -2932,8 +2948,9 @@ uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) uint32_t fsth2; set_float_exception_flags(0, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); - fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, + &env->active_fpu.fp_status); + fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status); update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } @@ -2944,7 +2961,7 @@ uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); - fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); + fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; } @@ -2955,7 +2972,7 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); update_fcr31(env); return fst2; } @@ -2968,8 +2985,8 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); - fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); + fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status); update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3078,7 +3095,8 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); - fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); + fdt2 = float64_chs(float64_sub(fdt2, float64_one, + &env->active_fpu.fp_status)); update_fcr31(env); return fdt2; } @@ -3087,7 +3105,8 @@ uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); + fst2 = float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); update_fcr31(env); return fst2; } @@ -3102,8 +3121,10 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); - fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); + fst2 = float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); + fsth2 = float32_chs(float32_sub(fsth2, float32_one, + &env->active_fpu.fp_status)); update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3112,7 +3133,7 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); - fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); + fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); update_fcr31(env); return fdt2; @@ -3122,7 +3143,7 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); + fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); update_fcr31(env); return fst2; @@ -3138,8 +3159,8 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); - fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); + fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); + fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); update_fcr31(env);