From patchwork Tue Oct 9 20:30:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Aurelien Jarno X-Patchwork-Id: 190432 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id CADA72C0096 for ; Wed, 10 Oct 2012 07:31:18 +1100 (EST) Received: from localhost ([::1]:50905 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgSS-0003Us-7P for incoming@patchwork.ozlabs.org; Tue, 09 Oct 2012 16:31:16 -0400 Received: from eggs.gnu.org ([208.118.235.92]:50551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgS9-0003MN-Sz for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:31:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TLgS8-0006EB-LB for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:30:57 -0400 Received: from hall.aurel32.net ([88.191.126.93]:42134) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TLgS8-0006De-FL for qemu-devel@nongnu.org; Tue, 09 Oct 2012 16:30:56 -0400 Received: from [2001:470:d4ed:0:ea11:32ff:fea1:831a] (helo=ohm.aurel32.net) by hall.aurel32.net with esmtpsa (TLS1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.72) (envelope-from ) id 1TLgS7-00079y-8a; Tue, 09 Oct 2012 22:30:55 +0200 Received: from aurel32 by ohm.aurel32.net with local (Exim 4.80) (envelope-from ) id 1TLgS5-0005pD-Mn; Tue, 09 Oct 2012 22:30:53 +0200 From: Aurelien Jarno To: qemu-devel@nongnu.org Date: Tue, 9 Oct 2012 22:30:52 +0200 Message-Id: <1349814652-22325-6-git-send-email-aurelien@aurel32.net> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1349814652-22325-1-git-send-email-aurelien@aurel32.net> References: <1349814652-22325-1-git-send-email-aurelien@aurel32.net> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) X-Received-From: 88.191.126.93 Cc: Peter Maydell , Aurelien Jarno Subject: [Qemu-devel] [PATCH 5/5] tcg/arm: improve direct jump X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Use ldr pc, [pc, #-4] kind of branch for direct jump. This removes the need to flush the icache on TB linking, and allow to remove the limit on the code generation buffer. This improves the boot-up speed of a MIPS guest by 11%. Cc: Andrzej Zaborowski Cc: Peter Maydell Signed-off-by: Aurelien Jarno --- exec-all.h | 24 ++++-------------------- exec.c | 4 ---- tcg/arm/tcg-target.c | 7 +------ 3 files changed, 5 insertions(+), 30 deletions(-) diff --git a/exec-all.h b/exec-all.h index 6516da0..662b916 100644 --- a/exec-all.h +++ b/exec-all.h @@ -224,26 +224,10 @@ static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) #elif defined(__arm__) static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) { -#if !QEMU_GNUC_PREREQ(4, 1) - register unsigned long _beg __asm ("a1"); - register unsigned long _end __asm ("a2"); - register unsigned long _flg __asm ("a3"); -#endif - - /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ - *(uint32_t *)jmp_addr = - (*(uint32_t *)jmp_addr & ~0xffffff) - | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); - -#if QEMU_GNUC_PREREQ(4, 1) - __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); -#else - /* flush icache */ - _beg = jmp_addr; - _end = jmp_addr + 4; - _flg = 0; - __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); -#endif + /* Patch the branch destination. It uses a ldr pc, [pc, #-4] kind + of branch so we write absolute address and we don't need to + flush icache. */ + *(uint32_t *)jmp_addr = addr; } #elif defined(__sparc__) void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); diff --git a/exec.c b/exec.c index 7899042..8d115ac 100644 --- a/exec.c +++ b/exec.c @@ -546,10 +546,6 @@ static void code_gen_alloc(unsigned long tb_size) start = (void *) 0x40000000UL; if (code_gen_buffer_size > (512 * 1024 * 1024)) code_gen_buffer_size = (512 * 1024 * 1024); -#elif defined(__arm__) - /* Keep the buffer no bigger than 16MB to branch between blocks */ - if (code_gen_buffer_size > 16 * 1024 * 1024) - code_gen_buffer_size = 16 * 1024 * 1024; #elif defined(__s390x__) /* Map the buffer so that we can use direct calls and branches. */ /* We have a +- 4GB range on the branches; leave some slop. */ diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index fafbd5d..e04cfa7 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1501,14 +1501,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_goto_tb: if (s->tb_jmp_offset) { /* Direct jump method */ -#if defined(USE_DIRECT_JUMP) - s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; - tcg_out_b_noaddr(s, COND_AL); -#else tcg_out_ld32_12(s, COND_AL, TCG_REG_PC, TCG_REG_PC, -4); s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf; - tcg_out32(s, 0); -#endif + tcg_out32(s, (int)s->code_ptr + 4); } else { /* Indirect jump method */ #if 1