From patchwork Mon Oct 8 21:42:33 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 190144 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 2CFC02C01FD for ; Tue, 9 Oct 2012 08:47:29 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 615AE281C1; Mon, 8 Oct 2012 23:47:27 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Z4nlUB-ec-3h; Mon, 8 Oct 2012 23:47:27 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A7A42281C9; Mon, 8 Oct 2012 23:44:29 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2EC72281C0 for ; Mon, 8 Oct 2012 23:44:21 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tgFWnp+an49j for ; Mon, 8 Oct 2012 23:44:19 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-qc0-f202.google.com (mail-qc0-f202.google.com [209.85.216.202]) by theia.denx.de (Postfix) with ESMTPS id 664B728187 for ; Mon, 8 Oct 2012 23:44:11 +0200 (CEST) Received: by mail-qc0-f202.google.com with SMTP id s25so520140qcq.3 for ; Mon, 08 Oct 2012 14:44:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=UUbwa5blPiIYULkTH/AdUVZYprhQvc3+/pA1vsqMfmM=; b=E9JjOvjHkkov3Pn3nxdlKTjKBTdVQEDlWfHmz3KZDhWwLOG6ds2C1KgTwrT1BMCp04 fsWIw49SWwFZcS3XTU0lveozVq1msFQWd7Sy07SPB9GGptvPLfovWH3EwWHkAybDwjhG RocxAxqRgSIrR8YLep+wjety6SYY22Oz83wM7GKeCmXkaQjEdn6Ai0fk4sLRFaj/RrZ0 5qwW2bESKhF2RmnDkybuVUYK6VgeDiQhwQDYplBRBSW8cwuI354hTo+urXoN1zXbEP/B jvZOII43V2BFUqmM1LEl9m+bQKdMSZe8p1tLreaaPfOtsQpQhlA+/JlCwR83Y4czpKSs Xuew== Received: by 10.100.81.6 with SMTP id e6mr3198962anb.27.1349732650610; Mon, 08 Oct 2012 14:44:10 -0700 (PDT) Received: from wpzn3.hot.corp.google.com (216-239-44-65.google.com [216.239.44.65]) by gmr-mx.google.com with ESMTPS id y43si4442215yhi.2.2012.10.08.14.44.10 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 08 Oct 2012 14:44:10 -0700 (PDT) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by wpzn3.hot.corp.google.com (Postfix) with ESMTP id 6DC99100047; Mon, 8 Oct 2012 14:44:10 -0700 (PDT) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id 4C36E161C0A; Mon, 8 Oct 2012 14:44:10 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Mon, 8 Oct 2012 14:42:33 -0700 Message-Id: <1349732556-30700-14-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1349732556-30700-1-git-send-email-sjg@chromium.org> References: <1349732556-30700-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQkLlomY/13AW7nSwmTnR/u2Eeb70AAUvw+eA8J89sELVhZtvbyGY5aXe9p32KdROwMS0Xw+X5AqcpQG+4l9DTylH1anRv4xzIHpEYBz4V7PuHd7U3+ONC2dSDzK1P77T4UfxPdXbN/DVu5EF42gCHRa9XkuRZHoJyoho/vTQ82TzcNJO20//vDXLaM/D1QwLGpbBy3y Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH v5 13/16] tegra: Support control of cache settings for LCD X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add support for selecting the required cache mode for the LCD: off, write-through or write-back. Signed-off-by: Simon Glass --- Changes in v3: - Handle a cached frame buffer out of normal U-Boot memory drivers/video/tegra.c | 11 +++++++++++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/drivers/video/tegra.c b/drivers/video/tegra.c index 9df2bd3..ff2b70e 100644 --- a/drivers/video/tegra.c +++ b/drivers/video/tegra.c @@ -145,6 +145,7 @@ static void update_panel_size(struct fdt_disp_config *config) void lcd_ctrl_init(void *lcdbase) { int line_length, size; + int type = DCACHE_OFF; assert(disp_config); @@ -160,6 +161,16 @@ void lcd_ctrl_init(void *lcdbase) update_panel_size(disp_config); size = lcd_get_size(&line_length); + /* Set up the LCD caching as requested */ + if (config.cache_type & FDT_LCD_CACHE_WRITE_THROUGH) + type = DCACHE_WRITETHROUGH; + else if (config.cache_type & FDT_LCD_CACHE_WRITE_BACK) + type = DCACHE_WRITEBACK; + mmu_set_region_dcache(disp_config->frame_buffer, size, type); + + /* Enable flushing after LCD writes if requested */ + lcd_set_flush_dcache(config.cache_type & FDT_LCD_CACHE_FLUSH); + debug("LCD frame buffer at %p\n", lcd_base); }