From patchwork Mon Oct 8 21:42:22 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 190133 X-Patchwork-Delegate: twarren@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 745332C035C for ; Tue, 9 Oct 2012 08:44:37 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id A8B58281DD; Mon, 8 Oct 2012 23:44:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2MgcysyYScsI; Mon, 8 Oct 2012 23:44:35 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 231D3281A7; Mon, 8 Oct 2012 23:44:16 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 12F0A28191 for ; Mon, 8 Oct 2012 23:44:13 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Pe3AXFwvXW7S for ; Mon, 8 Oct 2012 23:44:12 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-fa0-f74.google.com (mail-fa0-f74.google.com [209.85.161.74]) by theia.denx.de (Postfix) with ESMTPS id 4259928186 for ; Mon, 8 Oct 2012 23:44:10 +0200 (CEST) Received: by mail-fa0-f74.google.com with SMTP id t1so284207fae.3 for ; Mon, 08 Oct 2012 14:44:10 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=/A6y/JxzB5GhiINNKPKlqwQpHhpwhu/+evROLBwRsEQ=; b=d9hqa419oTtO5OK1QGTfiGXd0LzWVPrJRHT3tY12gjFIKKCb2B90i9ANOU+1hzXL6m cCrpMCT5NUxEFQbBA3lyggAI36g4IMdGuwCGGZ5pDUXEFhiJgxvP4wA8D+InL0nvyD4D nlcpVot2J2Dh34ZxNNdbp5o8zY+9xXdAhD7ywnZo7ePX8NGH3SUWfcmY2/xPPSOt7A7I 6UzXdJDXyAxgIKrwerCQiNYC7ifsIcSj6dia/LDL2kgz+JmkKQ4R4+znIlOmthk+01sQ RY3mMDRA3shceVKDl5BzNGhmDhy6yarfFl+1DpgUXGixDKKzulYwtglVxInM6elCDsLZ UkZw== Received: by 10.180.105.41 with SMTP id gj9mr2728669wib.3.1349732650161; Mon, 08 Oct 2012 14:44:10 -0700 (PDT) Received: from hpza10.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id cx9si1102774wib.0.2012.10.08.14.44.10 (version=TLSv1/SSLv3 cipher=AES128-SHA); Mon, 08 Oct 2012 14:44:10 -0700 (PDT) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by hpza10.eem.corp.google.com (Postfix) with ESMTP id BF5DF20004E; Mon, 8 Oct 2012 14:44:09 -0700 (PDT) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id 1D19D1612A7; Mon, 8 Oct 2012 14:44:09 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Mon, 8 Oct 2012 14:42:22 -0700 Message-Id: <1349732556-30700-3-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1349732556-30700-1-git-send-email-sjg@chromium.org> References: <1349732556-30700-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQkStWMkHUXGVopREbdSExuXnjR4oPG5zMcS3GlQVYkjwROROBdB5SPpE/P5ZtjEf2jqQi7f+dYALKtTXwpWVv4a+nATEEZQFlZdkGAq3SWDzwWag6mVywgu6gaM2WWQIDiJwzfXi8JTfd2o0wkh79BdYcz0Kyo1CoceDKKucRwRikYycY7qweDDKVKcbwG4DsdmyZdj Cc: Stephen Warren , Tom Warren Subject: [U-Boot] [PATCH v5 02/16] tegra: Add display support to funcmux X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Add support for a default pin mapping for display1. Signed-off-by: Simon Glass --- Changes in v3: - Remove LPW1 pin which is not needed by display Changes in v2: - Use const where possible in funcmux arch/arm/cpu/tegra20-common/funcmux.c | 37 +++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) diff --git a/arch/arm/cpu/tegra20-common/funcmux.c b/arch/arm/cpu/tegra20-common/funcmux.c index b2129ad..ca20f93 100644 --- a/arch/arm/cpu/tegra20-common/funcmux.c +++ b/arch/arm/cpu/tegra20-common/funcmux.c @@ -25,6 +25,30 @@ #include #include +/* + * The PINMUX macro is used to set up pinmux tables. + */ +#define PINMUX(grp, mux, pupd, tri) \ + {PINGRP_##grp, PMUX_FUNC_##mux, PMUX_PULL_##pupd, PMUX_TRI_##tri} + +static const struct pingroup_config disp1_default[] = { + PINMUX(LDI, DISPA, NORMAL, NORMAL), + PINMUX(LHP0, DISPA, NORMAL, NORMAL), + PINMUX(LHP1, DISPA, NORMAL, NORMAL), + PINMUX(LHP2, DISPA, NORMAL, NORMAL), + PINMUX(LHS, DISPA, NORMAL, NORMAL), + PINMUX(LM0, RSVD4, NORMAL, NORMAL), + PINMUX(LPP, DISPA, NORMAL, NORMAL), + PINMUX(LPW0, DISPA, NORMAL, NORMAL), + PINMUX(LPW2, DISPA, NORMAL, NORMAL), + PINMUX(LSC0, DISPA, NORMAL, NORMAL), + PINMUX(LSPI, DISPA, NORMAL, NORMAL), + PINMUX(LVP1, DISPA, NORMAL, NORMAL), + PINMUX(LVS, DISPA, NORMAL, NORMAL), + PINMUX(SLXD, SPDIF, NORMAL, NORMAL), +}; + + int funcmux_select(enum periph_id id, int config) { int bad_config = config != FUNCMUX_DEFAULT; @@ -240,6 +264,19 @@ int funcmux_select(enum periph_id id, int config) pinmux_tristate_disable(PINGRP_ATC); } break; + case PERIPH_ID_DISP1: + if (config == FUNCMUX_DEFAULT) { + int i; + + for (i = PINGRP_LD0; i <= PINGRP_LD17; i++) { + pinmux_set_func(i, PMUX_FUNC_DISPA); + pinmux_tristate_disable(i); + pinmux_set_pullupdown(i, PMUX_PULL_NORMAL); + } + pinmux_config_table(disp1_default, + ARRAY_SIZE(disp1_default)); + } + break; default: debug("%s: invalid periph_id %d", __func__, id);