Patchwork [v2,1/2] ARM: imx: clk: Split SSI clock into 'ipg' and 'per'

login
register
mail settings
Submitter Fabio Estevam
Date Oct. 8, 2012, 7:40 p.m.
Message ID <1349725213-11354-1-git-send-email-fabio.estevam@freescale.com>
Download mbox | patch
Permalink /patch/190114/
State New
Headers show

Comments

Fabio Estevam - Oct. 8, 2012, 7:40 p.m.
Currently imx ssi driver has been using only the ipg clock as only slave mode
is supported.

For mx27 it is necessay to provide both 'ipg' and 'per' clocks in order to get
ssi functional.

This issue was found on mx27 by unselecting the mmc driver from the kernel
,which resulted on a system that could not play audio.

When the mmc driver is selected the required 'per2' clock is provided and it 
allows the ssi to work.

Add the required 'per' clock to the mx27 ssi and a dummy one for the other SoCs.

Reported-by: Gaëtan Carlier <gcembed@gmail.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v1:
- Drop per4 from the camera clok, which belonged to a different patch
 arch/arm/mach-imx/clk-imx21.c       |   11 +++++++----
 arch/arm/mach-imx/clk-imx25.c       |    6 ++++--
 arch/arm/mach-imx/clk-imx27.c       |    8 ++++----
 arch/arm/mach-imx/clk-imx31.c       |   11 +++++++----
 arch/arm/mach-imx/clk-imx35.c       |   10 +++++++---
 arch/arm/mach-imx/clk-imx51-imx53.c |   19 +++++++++++++------
 6 files changed, 42 insertions(+), 23 deletions(-)
Sascha Hauer - Oct. 8, 2012, 9:44 p.m.
On Mon, Oct 08, 2012 at 04:40:13PM -0300, Fabio Estevam wrote:
> Currently imx ssi driver has been using only the ipg clock as only slave mode
> is supported.
> 
> For mx27 it is necessay to provide both 'ipg' and 'per' clocks in order to get
> ssi functional.
> 
> This issue was found on mx27 by unselecting the mmc driver from the kernel
> ,which resulted on a system that could not play audio.
> 
> When the mmc driver is selected the required 'per2' clock is provided and it 
> allows the ssi to work.

I am not sure it's good to work around that issue in the ssi driver. We
could also just enable the clock in the clk driver as it seems to be a
ccm related issue.
According to the datasheet per2_clk has absolutely nothing to do with
the ssi unit. Are you really sure there is not another bug in the clk
driver triggering this behaviour?

BTW i.MX6 would need a fixup aswell.

Sascha

> 
> Add the required 'per' clock to the mx27 ssi and a dummy one for the other SoCs.
> 
> Reported-by: Gaëtan Carlier <gcembed@gmail.com>
> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
> ---
> Changes since v1:
> - Drop per4 from the camera clok, which belonged to a different patch
>  arch/arm/mach-imx/clk-imx21.c       |   11 +++++++----
>  arch/arm/mach-imx/clk-imx25.c       |    6 ++++--
>  arch/arm/mach-imx/clk-imx27.c       |    8 ++++----
>  arch/arm/mach-imx/clk-imx31.c       |   11 +++++++----
>  arch/arm/mach-imx/clk-imx35.c       |   10 +++++++---
>  arch/arm/mach-imx/clk-imx51-imx53.c |   19 +++++++++++++------
>  6 files changed, 42 insertions(+), 23 deletions(-)
> 
> diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
> index cf65148..2ed49c8 100644
> --- a/arch/arm/mach-imx/clk-imx21.c
> +++ b/arch/arm/mach-imx/clk-imx21.c
> @@ -51,8 +51,8 @@ static const char *mpll_sel_clks[] = { "fpm", "ckih", };
>  static const char *spll_sel_clks[] = { "fpm", "ckih", };
>  
>  enum imx21_clks {
> -	ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
> -	per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
> +	dummy, ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg,
> +	per1, per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
>  	uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
>  	pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
>  	lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
> @@ -72,6 +72,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
>  {
>  	int i;
>  
> +	clk[dummy] = imx_clk_fixed("dummy", 0);
>  	clk[ckil] = imx_clk_fixed("ckil", lref);
>  	clk[ckih] = imx_clk_fixed("ckih", href);
>  	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
> @@ -174,8 +175,10 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
>  	clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
>  	clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
>  	clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
> -	clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
> -	clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
> +	clk_register_clkdev(clk[ssi1_gate], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_gate], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
>  	clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
>  	clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
>  
> diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
> index d20d479..c81864d 100644
> --- a/arch/arm/mach-imx/clk-imx25.c
> +++ b/arch/arm/mach-imx/clk-imx25.c
> @@ -222,8 +222,10 @@ int __init mx25_clocks_init(void)
>  	clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
>  	clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
>  	clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
> -	clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
>  	clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
>  	clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
>  	clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
> diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
> index 3b6b640..8cbb6b5 100644
> --- a/arch/arm/mach-imx/clk-imx27.c
> +++ b/arch/arm/mach-imx/clk-imx27.c
> @@ -236,8 +236,10 @@ int __init mx27_clocks_init(unsigned long fref)
>  	clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
>  	clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
>  	clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
> -	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_ipg_gate], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_ipg_gate], "ipg", "imx-ssi.1");
> +	clk_register_clkdev(clk[per2_gate], "per", "imx-ssi.0");
> +	clk_register_clkdev(clk[per2_gate], "per", "imx-ssi.1");
>  	clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
>  	clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
>  	clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
> @@ -262,8 +264,6 @@ int __init mx27_clocks_init(unsigned long fref)
>  	clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
>  	clk_register_clkdev(clk[cpu_div], "cpu", NULL);
>  	clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
> -	clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
>  
>  	mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
>  
> diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
> index 1253af2..61567dc 100644
> --- a/arch/arm/mach-imx/clk-imx31.c
> +++ b/arch/arm/mach-imx/clk-imx31.c
> @@ -35,8 +35,8 @@ static const char *csi_sel[] = { "upll", "spll", };
>  static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
>  
>  enum mx31_clks {
> -	ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
> -	per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
> +	dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
> +	per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
>  	fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
>  	iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
>  	uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
> @@ -53,6 +53,7 @@ int __init mx31_clocks_init(unsigned long fref)
>  	void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
>  	int i;
>  
> +	clk[dummy] = imx_clk_fixed("dummy", 0);
>  	clk[ckih] = imx_clk_fixed("ckih", fref);
>  	clk[ckil] = imx_clk_fixed("ckil", 32768);
>  	clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
> @@ -161,8 +162,10 @@ int __init mx31_clocks_init(unsigned long fref)
>  	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
>  	clk_register_clkdev(clk[sdhc1_gate], NULL, "mxc-mmc.0");
>  	clk_register_clkdev(clk[sdhc2_gate], NULL, "mxc-mmc.1");
> -	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_gate], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_gate], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
>  	clk_register_clkdev(clk[firi_gate], "firi", NULL);
>  	clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
>  	clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
> diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
> index 177259b..1ab7467 100644
> --- a/arch/arm/mach-imx/clk-imx35.c
> +++ b/arch/arm/mach-imx/clk-imx35.c
> @@ -50,7 +50,7 @@ static const char *std_sel[] = {"ppll", "arm"};
>  static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
>  
>  enum mx35_clks {
> -	ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
> +	dummy, ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
>  	arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
>  	esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
>  	spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
> @@ -88,6 +88,7 @@ int __init mx35_clocks_init()
>  		aad = &clk_consumer[0];
>  	}
>  
> +	clk[dummy] = imx_clk_fixed("dummy", 0);
>  	clk[ckih] = imx_clk_fixed("ckih", 24000000);
>  	clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL);
>  	clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL);
> @@ -234,8 +235,11 @@ int __init mx35_clocks_init()
>  	clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
>  	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
>  	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
> -	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi1_gate], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_gate], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
> +
>  	/* i.mx35 has the i.mx21 type uart */
>  	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
>  	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
> diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
> index a0bf848..46d679c 100644
> --- a/arch/arm/mach-imx/clk-imx51-imx53.c
> +++ b/arch/arm/mach-imx/clk-imx51-imx53.c
> @@ -273,9 +273,12 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil,
>  	clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
>  	clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
>  	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
> -	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
> -	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
> -	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
> +	clk_register_clkdev(clk[ssi1_ipg_gate], "ipg", "imx-ssi.0");
> +	clk_register_clkdev(clk[ssi2_ipg_gate], "ipg", "imx-ssi.1");
> +	clk_register_clkdev(clk[ssi3_ipg_gate], "ipg", "imx-ssi.2");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
> +	clk_register_clkdev(clk[dummy], "per", "imx-ssi.2");
>  	clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
>  	clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
>  	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
> @@ -366,9 +369,13 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
>  	clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
>  	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
>  	clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
> -	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
> -	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
> -	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
> +	clk_register_clkdev(clk[ssi1_ipg_gate], "ipg", "83fcc000.ssi");
> +	clk_register_clkdev(clk[ssi2_ipg_gate], "ipg", "70014000.ssi");
> +	clk_register_clkdev(clk[ssi3_ipg_gate], "ipg", "83fe8000.ssi");
> +	clk_register_clkdev(clk[dummy], "per", "83fcc000.ssi");
> +	clk_register_clkdev(clk[dummy], "per", "70014000.ssi");
> +	clk_register_clkdev(clk[dummy], "per", "83fe8000.ssi");
> +
>  	clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
>  
>  	/* set the usboh3 parent to pll2_sw */
> -- 
> 1.7.9.5
> 
> 
>
Fabio Estevam - Oct. 8, 2012, 11:47 p.m.
Hi Sascha,

On Mon, Oct 8, 2012 at 6:44 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:

> I am not sure it's good to work around that issue in the ssi driver. We
> could also just enable the clock in the clk driver as it seems to be a
> ccm related issue.

Yes, it would be better if we could fix this in clk-imx27 instead, but
I was not able to provide such fix yet.

Regards,

Fabio Estevam
Fabio Estevam - Oct. 9, 2012, 4:21 a.m.
Sascha,

On Mon, Oct 8, 2012 at 8:47 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Sascha,
>
> On Mon, Oct 8, 2012 at 6:44 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
>> I am not sure it's good to work around that issue in the ssi driver. We
>> could also just enable the clock in the clk driver as it seems to be a
>> ccm related issue.
>
> Yes, it would be better if we could fix this in clk-imx27 instead, but
> I was not able to provide such fix yet.

The ssi1_sel clock is defined as:

clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks,
ARRAY_SIZE(ssi_sel_clks));

,where ssi_sel_clks is:
static const char *ssi_sel_clks[] = { "spll", "mpll", }

,which matches with the mx27 reference manual.

How do we tell the clk api to select spll or mpll as the source for ssi_sel?

I understand how to do this from register level, but not from the api.

Thanks,

Fabio Estevam
Sascha Hauer - Oct. 9, 2012, 7:11 a.m.
On Tue, Oct 09, 2012 at 01:21:10AM -0300, Fabio Estevam wrote:
> Sascha,
> 
> On Mon, Oct 8, 2012 at 8:47 PM, Fabio Estevam <festevam@gmail.com> wrote:
> > Hi Sascha,
> >
> > On Mon, Oct 8, 2012 at 6:44 PM, Sascha Hauer <s.hauer@pengutronix.de> wrote:
> >
> >> I am not sure it's good to work around that issue in the ssi driver. We
> >> could also just enable the clock in the clk driver as it seems to be a
> >> ccm related issue.
> >
> > Yes, it would be better if we could fix this in clk-imx27 instead, but
> > I was not able to provide such fix yet.
> 
> The ssi1_sel clock is defined as:
> 
> clk[ssi1_sel] = imx_clk_mux("ssi1_sel", CCM_CSCR, 22, 1, ssi_sel_clks,
> ARRAY_SIZE(ssi_sel_clks));
> 
> ,where ssi_sel_clks is:
> static const char *ssi_sel_clks[] = { "spll", "mpll", }
> 
> ,which matches with the mx27 reference manual.
> 
> How do we tell the clk api to select spll or mpll as the source for ssi_sel?
> 
> I understand how to do this from register level, but not from the api.

In the clk driver you can do a clk_set_parent(clk[ssi1_sel], clk[mpll]);

I wonder what the parent setting has to do with this problem. Could you
come up with a minimum patch to clk-imx27.c which fixes the problem?
Then we can discuss afterwards how to integrate it properly (or not the
least dirty).

Right now the clk framework has been succesful in turning the clk mess
into a proper tree. There currently is no API to manipulate that tree
in a non painful way. That would be the next steps.

Sascha

Patch

diff --git a/arch/arm/mach-imx/clk-imx21.c b/arch/arm/mach-imx/clk-imx21.c
index cf65148..2ed49c8 100644
--- a/arch/arm/mach-imx/clk-imx21.c
+++ b/arch/arm/mach-imx/clk-imx21.c
@@ -51,8 +51,8 @@  static const char *mpll_sel_clks[] = { "fpm", "ckih", };
 static const char *spll_sel_clks[] = { "fpm", "ckih", };
 
 enum imx21_clks {
-	ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg, per1,
-	per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
+	dummy, ckil, ckih, fpm, mpll_sel, spll_sel, mpll, spll, fclk, hclk, ipg,
+	per1, per2, per3, per4, uart1_ipg_gate, uart2_ipg_gate, uart3_ipg_gate,
 	uart4_ipg_gate, gpt1_ipg_gate, gpt2_ipg_gate, gpt3_ipg_gate,
 	pwm_ipg_gate, sdhc1_ipg_gate, sdhc2_ipg_gate, lcdc_ipg_gate,
 	lcdc_hclk_gate, cspi3_ipg_gate, cspi2_ipg_gate, cspi1_ipg_gate,
@@ -72,6 +72,7 @@  int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 {
 	int i;
 
+	clk[dummy] = imx_clk_fixed("dummy", 0);
 	clk[ckil] = imx_clk_fixed("ckil", lref);
 	clk[ckih] = imx_clk_fixed("ckih", href);
 	clk[fpm] = imx_clk_fixed_factor("fpm", "ckil", 512, 1);
@@ -174,8 +175,10 @@  int __init mx21_clocks_init(unsigned long lref, unsigned long href)
 	clk_register_clkdev(clk[gpio_gate], "gpio", NULL);
 	clk_register_clkdev(clk[rtc_gate], "rtc", NULL);
 	clk_register_clkdev(clk[csi_hclk_gate], "csi", NULL);
-	clk_register_clkdev(clk[ssi1_gate], "ssi1", NULL);
-	clk_register_clkdev(clk[ssi2_gate], "ssi2", NULL);
+	clk_register_clkdev(clk[ssi1_gate], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_gate], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
 	clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
 	clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
 
diff --git a/arch/arm/mach-imx/clk-imx25.c b/arch/arm/mach-imx/clk-imx25.c
index d20d479..c81864d 100644
--- a/arch/arm/mach-imx/clk-imx25.c
+++ b/arch/arm/mach-imx/clk-imx25.c
@@ -222,8 +222,10 @@  int __init mx25_clocks_init(void)
 	clk_register_clkdev(clk[lcdc_ipg], "ipg", "imx-fb.0");
 	clk_register_clkdev(clk[lcdc_ahb], "ahb", "imx-fb.0");
 	clk_register_clkdev(clk[wdt_ipg], NULL, "imx2-wdt.0");
-	clk_register_clkdev(clk[ssi1_ipg], NULL, "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_ipg], NULL, "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_ipg], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_ipg], "ipg", "imx-ssi.1");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
 	clk_register_clkdev(clk[esdhc1_ipg_per], "per", "sdhci-esdhc-imx25.0");
 	clk_register_clkdev(clk[esdhc1_ipg], "ipg", "sdhci-esdhc-imx25.0");
 	clk_register_clkdev(clk[esdhc1_ahb], "ahb", "sdhci-esdhc-imx25.0");
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 3b6b640..8cbb6b5 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -236,8 +236,10 @@  int __init mx27_clocks_init(unsigned long fref)
 	clk_register_clkdev(clk[usb_div], "per", "mxc-ehci.2");
 	clk_register_clkdev(clk[usb_ipg_gate], "ipg", "mxc-ehci.2");
 	clk_register_clkdev(clk[usb_ahb_gate], "ahb", "mxc-ehci.2");
-	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_ipg_gate], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_ipg_gate], "ipg", "imx-ssi.1");
+	clk_register_clkdev(clk[per2_gate], "per", "imx-ssi.0");
+	clk_register_clkdev(clk[per2_gate], "per", "imx-ssi.1");
 	clk_register_clkdev(clk[nfc_baud_gate], NULL, "mxc_nand.0");
 	clk_register_clkdev(clk[vpu_baud_gate], "per", "coda-imx27.0");
 	clk_register_clkdev(clk[vpu_ahb_gate], "ahb", "coda-imx27.0");
@@ -262,8 +264,6 @@  int __init mx27_clocks_init(unsigned long fref)
 	clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
 	clk_register_clkdev(clk[cpu_div], "cpu", NULL);
 	clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
-	clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
 
 	mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
 
diff --git a/arch/arm/mach-imx/clk-imx31.c b/arch/arm/mach-imx/clk-imx31.c
index 1253af2..61567dc 100644
--- a/arch/arm/mach-imx/clk-imx31.c
+++ b/arch/arm/mach-imx/clk-imx31.c
@@ -35,8 +35,8 @@  static const char *csi_sel[] = { "upll", "spll", };
 static const char *fir_sel[] = { "mcu_main", "upll", "spll" };
 
 enum mx31_clks {
-	ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg, per_div,
-	per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
+	dummy, ckih, ckil, mpll, spll, upll, mcu_main, hsp, ahb, nfc, ipg,
+	per_div, per, csi, fir, csi_div, usb_div_pre, usb_div_post, fir_div_pre,
 	fir_div_post, sdhc1_gate, sdhc2_gate, gpt_gate, epit1_gate, epit2_gate,
 	iim_gate, ata_gate, sdma_gate, cspi3_gate, rng_gate, uart1_gate,
 	uart2_gate, ssi1_gate, i2c1_gate, i2c2_gate, i2c3_gate, hantro_gate,
@@ -53,6 +53,7 @@  int __init mx31_clocks_init(unsigned long fref)
 	void __iomem *base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
 	int i;
 
+	clk[dummy] = imx_clk_fixed("dummy", 0);
 	clk[ckih] = imx_clk_fixed("ckih", fref);
 	clk[ckil] = imx_clk_fixed("ckil", 32768);
 	clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MXC_CCM_MPCTL);
@@ -161,8 +162,10 @@  int __init mx31_clocks_init(unsigned long fref)
 	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1.0");
 	clk_register_clkdev(clk[sdhc1_gate], NULL, "mxc-mmc.0");
 	clk_register_clkdev(clk[sdhc2_gate], NULL, "mxc-mmc.1");
-	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_gate], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_gate], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
 	clk_register_clkdev(clk[firi_gate], "firi", NULL);
 	clk_register_clkdev(clk[ata_gate], NULL, "pata_imx");
 	clk_register_clkdev(clk[rtic_gate], "rtic", NULL);
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index 177259b..1ab7467 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -50,7 +50,7 @@  static const char *std_sel[] = {"ppll", "arm"};
 static const char *ipg_per_sel[] = {"ahb_per_div", "arm_per_div"};
 
 enum mx35_clks {
-	ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
+	dummy, ckih, mpll, ppll, mpll_075, arm, hsp, hsp_div, hsp_sel, ahb, ipg,
 	arm_per_div, ahb_per_div, ipg_per, uart_sel, uart_div, esdhc_sel,
 	esdhc1_div, esdhc2_div, esdhc3_div, spdif_sel, spdif_div_pre,
 	spdif_div_post, ssi_sel, ssi1_div_pre, ssi1_div_post, ssi2_div_pre,
@@ -88,6 +88,7 @@  int __init mx35_clocks_init()
 		aad = &clk_consumer[0];
 	}
 
+	clk[dummy] = imx_clk_fixed("dummy", 0);
 	clk[ckih] = imx_clk_fixed("ckih", 24000000);
 	clk[mpll] = imx_clk_pllv1("mpll", "ckih", base + MX35_CCM_MPCTL);
 	clk[ppll] = imx_clk_pllv1("ppll", "ckih", base + MX35_CCM_PPCTL);
@@ -234,8 +235,11 @@  int __init mx35_clocks_init()
 	clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
 	clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
 	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
-	clk_register_clkdev(clk[ssi1_gate], NULL, "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_gate], NULL, "imx-ssi.1");
+	clk_register_clkdev(clk[ssi1_gate], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_gate], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
+
 	/* i.mx35 has the i.mx21 type uart */
 	clk_register_clkdev(clk[uart1_gate], "per", "imx21-uart.0");
 	clk_register_clkdev(clk[ipg], "ipg", "imx21-uart.0");
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index a0bf848..46d679c 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -273,9 +273,12 @@  static void __init mx5_clocks_common_init(unsigned long rate_ckil,
 	clk_register_clkdev(clk[usboh3_gate], "ipg", "fsl-usb2-udc");
 	clk_register_clkdev(clk[usboh3_gate], "ahb", "fsl-usb2-udc");
 	clk_register_clkdev(clk[nfc_gate], NULL, "mxc_nand");
-	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "imx-ssi.0");
-	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "imx-ssi.1");
-	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "imx-ssi.2");
+	clk_register_clkdev(clk[ssi1_ipg_gate], "ipg", "imx-ssi.0");
+	clk_register_clkdev(clk[ssi2_ipg_gate], "ipg", "imx-ssi.1");
+	clk_register_clkdev(clk[ssi3_ipg_gate], "ipg", "imx-ssi.2");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.0");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.1");
+	clk_register_clkdev(clk[dummy], "per", "imx-ssi.2");
 	clk_register_clkdev(clk[ssi_ext1_gate], "ssi_ext1", NULL);
 	clk_register_clkdev(clk[ssi_ext2_gate], "ssi_ext2", NULL);
 	clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
@@ -366,9 +369,13 @@  int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
 	clk_register_clkdev(clk[esdhc4_ipg_gate], "ipg", "sdhci-esdhc-imx51.3");
 	clk_register_clkdev(clk[dummy], "ahb", "sdhci-esdhc-imx51.3");
 	clk_register_clkdev(clk[esdhc4_per_gate], "per", "sdhci-esdhc-imx51.3");
-	clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "83fcc000.ssi");
-	clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "70014000.ssi");
-	clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "83fe8000.ssi");
+	clk_register_clkdev(clk[ssi1_ipg_gate], "ipg", "83fcc000.ssi");
+	clk_register_clkdev(clk[ssi2_ipg_gate], "ipg", "70014000.ssi");
+	clk_register_clkdev(clk[ssi3_ipg_gate], "ipg", "83fe8000.ssi");
+	clk_register_clkdev(clk[dummy], "per", "83fcc000.ssi");
+	clk_register_clkdev(clk[dummy], "per", "70014000.ssi");
+	clk_register_clkdev(clk[dummy], "per", "83fe8000.ssi");
+
 	clk_register_clkdev(clk[nfc_gate], NULL, "83fdb000.nand");
 
 	/* set the usboh3 parent to pll2_sw */