Patchwork [U-Boot,28/28] powerpc/mpc85xx: Add CONFIG_DDR_CLK_FREQ for corenet platform

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Submitter York Sun
Date Oct. 8, 2012, 5:44 p.m.
Message ID <1349718271-26503-28-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/190096/
State Accepted, archived
Delegated to: Andy Fleming
Headers show

Comments

York Sun - Oct. 8, 2012, 5:44 p.m.
New corenet platforms with chassis2 have separated DDR clock inputs. Use
CONFIG_DDR_CLK_FREQ for DDR clock. This patch also cleans up the logic of
detecting and displaying synchronous vs asynchronous mode.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cpu.c   |   26 ++++++++++++++++----------
 arch/powerpc/cpu/mpc85xx/speed.c |    4 ++++
 2 files changed, 20 insertions(+), 10 deletions(-)

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 95f435e..24a572c 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -60,26 +60,32 @@  int checkcpu (void)
 	uint major, minor;
 	struct cpu_type *cpu;
 	char buf1[32], buf2[32];
-#if defined(CONFIG_DDR_CLK_FREQ) || \
-	(defined(CONFIG_FSL_CORENET) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2))
+#if (defined(CONFIG_DDR_CLK_FREQ) || \
+	defined(CONFIG_FSL_CORENET)) && !defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2)
 	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif /* CONFIG_FSL_CORENET */
-#ifdef CONFIG_DDR_CLK_FREQ
-	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
-		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
-#else
+
+	/*
+	 * Cornet platforms use ddr sync bit in RCW to indicate sync vs async
+	 * mode. Previous platform use ddr ratio to do the same. This
+	 * information is only for display here.
+	 */
 #ifdef CONFIG_FSL_CORENET
-	u32 ddr_sync ;
 #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2
-	ddr_sync = 0;	/* only async mode is supported */
+	u32 ddr_sync = 0;	/* only async mode is supported */
 #else
-	ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
+	u32 ddr_sync = ((gur->rcwsr[5]) & FSL_CORENET_RCWSR5_DDR_SYNC)
 		>> FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT;
 #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
+#else	/* CONFIG_FSL_CORENET */
+#ifdef CONFIG_DDR_CLK_FREQ
+	u32 ddr_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_DDR_RATIO)
+		>> MPC85xx_PORPLLSR_DDR_RATIO_SHIFT;
 #else
 	u32 ddr_ratio = 0;
-#endif /* CONFIG_FSL_CORENET */
 #endif /* CONFIG_DDR_CLK_FREQ */
+#endif /* CONFIG_FSL_CORENET */
+
 	unsigned int i, core, nr_cores = cpu_numcores();
 	u32 mask = cpu_mask();
 
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index 761441f..8bbf0bc 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -82,7 +82,11 @@  void get_sys_info (sys_info_t * sysInfo)
 	uint mem_pll_rat;
 
 	sysInfo->freqSystemBus = sysclk;
+#ifdef CONFIG_DDR_CLK_FREQ
+	sysInfo->freqDDRBus = CONFIG_DDR_CLK_FREQ;
+#else
 	sysInfo->freqDDRBus = sysclk;
+#endif
 
 	sysInfo->freqSystemBus *= (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
 	mem_pll_rat = (in_be32(&gur->rcwsr[0]) >>