Patchwork [U-Boot,23/28] powerpc/mpc85xx: Add workaround for DDR erratum A004934

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Submitter York Sun
Date Oct. 8, 2012, 5:44 p.m.
Message ID <1349718271-26503-23-git-send-email-yorksun@freescale.com>
Download mbox | patch
Permalink /patch/190095/
State Accepted, archived
Delegated to: Andy Fleming
Headers show

Comments

York Sun - Oct. 8, 2012, 5:44 p.m.
After DDR controller is enabled, it performs a calibration for the
transmit data vs DQS paths. During this calibration, the DDR controller
may make an inaccurate calculation, resulting in a non-optimal tap point.

Signed-off-by: York Sun <yorksun@freescale.com>
---
 arch/powerpc/cpu/mpc85xx/cmd_errata.c     |    3 +++
 arch/powerpc/cpu/mpc85xx/ddr-gen3.c       |    3 +++
 arch/powerpc/include/asm/config_mpc85xx.h |    1 +
 3 files changed, 7 insertions(+)

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 67508ff..4b62651 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -130,6 +130,9 @@  static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 #ifdef CONFIG_SYS_FSL_ERRATUM_A004510
 	puts("Work-around for Erratum A004510 enabled\n");
 #endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+	puts("Work-around for Erratum A004934 enabled\n");
+#endif
 	return 0;
 }
 
diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index 8bed5fe..21840bf 100644
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -140,6 +140,9 @@  void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 			out_be32(&ddr->debug[i], regs->debug[i]);
 		}
 	}
+#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
+	out_be32(&ddr->debug[28], 0x00003000);
+#endif
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003474
 	out_be32(&ddr->debug[12], 0x00000015);
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index 225d620..0bbbf30 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -479,6 +479,7 @@ 
 #define CONFIG_SYS_FSL_USB2_PHY_ENABLE
 #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
 #define CONFIG_SYS_FSL_ERRATUM_A004468
+#define CONFIG_SYS_FSL_ERRATUM_A_004934
 #define CONFIG_SYS_CCSRBAR_DEFAULT	0xfe000000
 
 #elif defined(CONFIG_PPC_B4860)