From patchwork Mon Oct 8 17:44:12 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot, 09/28] powerpc/mpc85xx: expand SERDES reference clock select bit Date: Mon, 08 Oct 2012 07:44:12 -0000 From: York Sun X-Patchwork-Id: 190069 Message-Id: <1349718271-26503-9-git-send-email-yorksun@freescale.com> To: Cc: afleming@freescale.com Expand the reference clock select to three bits 000: 100 MHz 001: 125 MHz 010: 156.25MHz 011: 150 MHz 100: 161.1328125 MHz All others reserved Signed-off-by: York Sun --- arch/powerpc/include/asm/immap_85xx.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7616d16..1b1db16 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2403,11 +2403,12 @@ typedef struct serdes_corenet { #define SRDS_RSTCTL_RSTERR 0x20000000 #define SRDS_RSTCTL_SDPD 0x00000020 u32 pllcr0; /* PLL Control Register 0 */ -#define SRDS_PLLCR0_RFCK_SEL_MASK 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_MASK 0x70000000 #define SRDS_PLLCR0_RFCK_SEL_100 0x00000000 #define SRDS_PLLCR0_RFCK_SEL_125 0x10000000 #define SRDS_PLLCR0_RFCK_SEL_156_25 0x20000000 #define SRDS_PLLCR0_RFCK_SEL_150 0x30000000 +#define SRDS_PLLCR0_RFCK_SEL_161_13 0x40000000 #define SRDS_PLLCR0_FRATE_SEL_MASK 0x00030000 #define SRDS_PLLCR0_FRATE_SEL_5 0x00000000 #define SRDS_PLLCR0_FRATE_SEL_6_25 0x00010000