From patchwork Mon Oct 8 10:26:18 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [4/7] ARM: tegra30: common: enable csite clock Date: Mon, 08 Oct 2012 00:26:18 -0000 From: Joseph Lo X-Patchwork-Id: 189975 Message-Id: <1349691981-31038-5-git-send-email-josephl@nvidia.com> To: Stephen Warren Cc: , , Joseph Lo Enable csite (debug and trace controller) clock at init to prevent it be disabled. And this also the necessary clock for CPU be brought up or resumed from a power-gate low power state (e.g., LP2). Signed-off-by: Joseph Lo --- arch/arm/mach-tegra/common.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c index 0b0a5f5..4a2dd98 100644 --- a/arch/arm/mach-tegra/common.c +++ b/arch/arm/mach-tegra/common.c @@ -104,6 +104,7 @@ static __initdata struct tegra_clk_init_table tegra30_clk_init_table[] = { { "clk_m", NULL, 0, true }, { "pll_p", "clk_m", 408000000, true }, { "pll_p_out1", "pll_p", 9600000, true }, + { "csite", NULL, 0, true }, { NULL, NULL, 0, 0}, }; #endif