From patchwork Mon Oct 8 04:18:25 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 189896 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 3742E2C01C6 for ; Mon, 8 Oct 2012 16:05:25 +1100 (EST) Received: from localhost ([::1]:42978 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL5Wr-0006xz-QT for incoming@patchwork.ozlabs.org; Mon, 08 Oct 2012 01:05:21 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33946) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL4p5-0003lc-5g for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:20:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TL4p2-00071r-Qb for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:20:07 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:64196) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL4p2-0006Z2-K5 for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:20:04 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so3690214pbb.4 for ; Sun, 07 Oct 2012 21:20:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=trkLQQDy8SbRSevOBZ957tPQGt8Ry38XZdbLJJPHF1Q=; b=fZMXch2e33ZMtKGjfHOnuZsikPYm7/0R0y4DqAvUR5G9k/dilZ4meQ1QEBQ5Wbe7HU 6+m67nYXDTlf5nyZ5uISAg2sNL1w1eukkz4qwFByiaEs0tf53/BdeU8gpbYi3QC4h3wV SFh+k1gxowDHf1uJgcURj9wgvc/zeDawTejtDzFCOYslvQxdbGvQuwqCx9oetHQqZnad NWJFRTrH7eTO6xE4Db6Tm12U8MWRHwZiUppQ3JTgdJuCpuD45LCry8bQqEBXNzRz4g+Z Do2sAx2OrHWZKXT8c68Ng5OoBBTYGCmSARpKKtS7BOHyxfesTcchYDcr/NYc4HeTBHMe WOQg== Received: by 10.68.211.67 with SMTP id na3mr43978416pbc.21.1349670003358; Sun, 07 Oct 2012 21:20:03 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id ky6sm10064080pbc.18.2012.10.07.21.20.00 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 07 Oct 2012 21:20:02 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com, peter.maydell@linaro.org Date: Mon, 8 Oct 2012 14:18:25 +1000 Message-Id: <2f78a6af6b85ac5acafceec7ab8fb679b2c9b72c.1349663471.git.peter.crosthwaite@xilinx.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQmdyPzGkTWiYAKc7iC5mp3lTL0zo+9gyrxnKbjiDy1HHG0i+P1y9WjT/yg5zLRe5gdBw+rF X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: "Peter A. G. Crosthwaite" Subject: [Qemu-devel] [PATCH v9 11/13] xilinx_zynq: Added SPI controllers + flashes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite Added the two SPI controllers to the zynq machine model. Attached two SPI flash devices to each controller. Signed-off-by: Peter A. G. Crosthwaite Acked-by: Peter Maydell --- changed from v7: Increased number of spi flashes pre controller to 4 changed from v6: removed (char*) cast to qdev_prop_set_string argument hw/xilinx_zynq.c | 34 ++++++++++++++++++++++++++++++++++ 1 files changed, 34 insertions(+), 0 deletions(-) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 7e6c273..fd46ba2 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -24,6 +24,9 @@ #include "flash.h" #include "blockdev.h" #include "loader.h" +#include "ssi.h" + +#define NUM_SPI_FLASHES 4 #define FLASH_SIZE (64 * 1024 * 1024) #define FLASH_SECTOR_SIZE (128 * 1024) @@ -46,6 +49,34 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_irq irq) sysbus_connect_irq(s, 0, irq); } +static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq) +{ + DeviceState *dev; + SysBusDevice *busdev; + SSIBus *spi; + int i; + + dev = qdev_create(NULL, "xilinx,spips"); + qdev_init_nofail(dev); + busdev = sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, base_addr); + sysbus_connect_irq(busdev, 0, irq); + + spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); + + for (i = 0; i < NUM_SPI_FLASHES; ++i) { + qemu_irq cs_line; + + dev = ssi_create_slave_no_init(spi, "m25p80"); + qdev_prop_set_string(dev, "partname", "n25q128"); + qdev_init_nofail(dev); + + cs_line = qdev_get_gpio_in(dev, 0); + sysbus_connect_irq(busdev, i+1, cs_line); + } + +} + static void zynq_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) @@ -113,6 +144,9 @@ static void zynq_init(ram_addr_t ram_size, const char *boot_device, pic[n] = qdev_get_gpio_in(dev, n); } + zynq_init_spi_flashes(0xE0006000, pic[58-IRQ_OFFSET]); + zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET]); + sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]);