From patchwork Mon Oct 8 04:18:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 189895 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id C4ECA2C01D3 for ; Mon, 8 Oct 2012 16:05:02 +1100 (EST) Received: from localhost ([::1]:41315 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL5WV-00060S-Bg for incoming@patchwork.ozlabs.org; Mon, 08 Oct 2012 01:04:59 -0400 Received: from eggs.gnu.org ([208.118.235.92]:33914) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL4or-0003Lp-DC for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:19:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TL4oq-0006tt-9y for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:19:53 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:64196) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TL4oq-0006Z2-3a for qemu-devel@nongnu.org; Mon, 08 Oct 2012 00:19:52 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so3690214pbb.4 for ; Sun, 07 Oct 2012 21:19:51 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=dIQPNlsD9Ow1i30eItVfCNPvT+kb/yMIlRtDaZrWOBk=; b=Mx7cVOvoCN9mTXW2ulv9nkiBdunnR8TY2CzsDsGUoGt9gZFVFWxQHFk7Hy2Jm04kU7 GZCnEVvpun7VOTdTeV4G8LkgQfZ2BdBl8ZUTqTsC6kJ/8GxjLSjLY9aCZyf7cFkG0WHC 5p80yEyFVK0KC/6oH0Br/mzUSEeIHxrC3putt3K+1fG7LJFYvSox8Wzs7hc0O4nZzayS Al5e+CB8YgbcB2lDDJie/ZnpqRsDUwYzq8pcABGxdL6AWxcJEul9KKkaxwc+6wwGtCGt zIKYxquhoqNZKM14phvi2XZ3/sgFQdomlnzq6myZnbp3qz1kIl8LX+XMR7+oFGMl1ygB Yt2A== Received: by 10.68.200.227 with SMTP id jv3mr49673627pbc.162.1349669991792; Sun, 07 Oct 2012 21:19:51 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id sj5sm10060585pbc.30.2012.10.07.21.19.49 (version=TLSv1/SSLv3 cipher=OTHER); Sun, 07 Oct 2012 21:19:51 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, edgar.iglesias@gmail.com, peter.maydell@linaro.org Date: Mon, 8 Oct 2012 14:18:23 +1000 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQnvD0KrkATrm6+SzBR9RQmSyIYviJ/Z4Wphd2gp29P4i8Qtw8GquW4qmWw7DM+S7WESRDo+ X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: "Peter A. G. Crosthwaite" Subject: [Qemu-devel] [PATCH v9 09/13] petalogix-ml605: added SPI controller with n25q128 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite Added SPI controller to the reference design, with two n25q128 spi-flashes connected. Signed-off-by: Peter A. G. Crosthwaite Acked-by: Peter Maydell --- Changed since v7: Increased number of spi flashes to 4 Fixed spi controller qdev name and property names (see prev patch) Changed since v5: Removed redundant (char*) cast with qdev_get_prop_string hw/petalogix_ml605_mmu.c | 27 +++++++++++++++++++++++++++ 1 files changed, 27 insertions(+), 0 deletions(-) diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index dced648..b9bfbed 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -36,6 +36,7 @@ #include "blockdev.h" #include "pc.h" #include "exec-memory.h" +#include "ssi.h" #include "microblaze_boot.h" #include "microblaze_pic_cpu.h" @@ -47,6 +48,8 @@ #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb" +#define NUM_SPI_FLASHES 4 + #define MEMORY_BASEADDR 0x50000000 #define FLASH_BASEADDR 0x86000000 #define INTC_BASEADDR 0x81800000 @@ -79,6 +82,7 @@ petalogix_ml605_init(ram_addr_t ram_size, MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev, *dma, *eth0; MicroBlazeCPU *cpu; + SysBusDevice *busdev; CPUMBState *env; DriveInfo *dinfo; int i; @@ -139,6 +143,29 @@ petalogix_ml605_init(ram_addr_t ram_size, xilinx_axiethernetdma_init(dma, STREAM_SLAVE(eth0), 0x84600000, irq[1], irq[0], 100 * 1000000); + { + SSIBus *spi; + + dev = qdev_create(NULL, "xlnx.xps-spi"); + qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); + qdev_init_nofail(dev); + busdev = sysbus_from_qdev(dev); + sysbus_mmio_map(busdev, 0, 0x40a00000); + sysbus_connect_irq(busdev, 0, irq[4]); + + spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); + + for (i = 0; i < NUM_SPI_FLASHES; i++) { + qemu_irq cs_line; + + dev = ssi_create_slave_no_init(spi, "m25p80"); + qdev_prop_set_string(dev, "partname", "n25q128"); + qdev_init_nofail(dev); + cs_line = qdev_get_gpio_in(dev, 0); + sysbus_connect_irq(busdev, i+1, cs_line); + } + } + microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, machine_cpu_reset);