From patchwork Sun Oct 7 11:43:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chander Kashyap X-Patchwork-Id: 189809 X-Patchwork-Delegate: promsoft@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 35B822C0180 for ; Sun, 7 Oct 2012 22:43:41 +1100 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 2387228094; Sun, 7 Oct 2012 13:43:39 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 6RN7Gq5VXMF1; Sun, 7 Oct 2012 13:43:38 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3527628089; Sun, 7 Oct 2012 13:43:37 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 56D7728089 for ; Sun, 7 Oct 2012 13:43:35 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id c2mw52v2o6Uy for ; Sun, 7 Oct 2012 13:43:34 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-da0-f44.google.com (mail-da0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 2607528087 for ; Sun, 7 Oct 2012 13:43:32 +0200 (CEST) Received: by mail-da0-f44.google.com with SMTP id h15so1111244dan.3 for ; Sun, 07 Oct 2012 04:43:29 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:x-gm-message-state; bh=veeGumf1bSRL/oPDuqWjTQu2cYiq6CKTqRn2YXndJ40=; b=onWQ04fwUgyjZF6nA82C4hKzekuNc7Th/RAFkVAWwM+O/nci0vsc2B9mmx0UI5d5OM GgLWZ3CANpdPot/G6EKBFI6nWxADN3XqhJ0OESPCvAhcFxncs7Ip71wyZOOylcrL1SyQ KWfWTQZJ8ZsUttfh9b9RedJt5VbI9rysL1oQdk+vMi90Vy+nAW2QguxTTxaUNMbmCjlp EyMqMxLBT9h+JOmExq8bQ1TVE4CIBYPqDxTvzVg7fmkh7cfMBVcOAWJYB0t6j8lNVfTO E9ohPdGT/lxr8L4B/8BbLvjGJ+Sxsbbrbff9aJw65ByLeEqatNz6FNcUbqWKttRpnFJa rKlA== Received: by 10.68.235.71 with SMTP id uk7mr45082397pbc.10.1349610209495; Sun, 07 Oct 2012 04:43:29 -0700 (PDT) Received: from localhost.localdomain ([115.113.119.130]) by mx.google.com with ESMTPS id qq1sm8803306pbc.74.2012.10.07.04.43.27 (version=SSLv3 cipher=OTHER); Sun, 07 Oct 2012 04:43:29 -0700 (PDT) From: Chander Kashyap To: u-boot@lists.denx.de Date: Sun, 7 Oct 2012 17:13:17 +0530 Message-Id: <1349610197-25957-1-git-send-email-chander.kashyap@linaro.org> X-Mailer: git-send-email 1.7.9.5 X-Gm-Message-State: ALoCoQm/YQhMGKExS3s1C5mRVLm/ei4pxYXLrdduDTYlNy9dOG9TXtWkT0cQI0cg2yMkuo/Ykr+P Cc: patches@linaro.org Subject: [U-Boot] [PATCH] EXYNOS: EXYNOS4X12: extract Exynos4x12 IPs clock frequency X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Adds functions to extract clock frequency of Exynos4x12 IPs. Signed-off-by: Chander Kashyap --- arch/arm/cpu/armv7/exynos/clock.c | 163 +++++++++++++++++++++++++++++++++++-- 1 file changed, 158 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index a042423..012beab 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -100,6 +100,36 @@ static unsigned long exynos4_get_pll_clk(int pllreg) return exynos_get_pll_clk(pllreg, r, k); } +/* exynos4x12: return pll clock frequency */ +static unsigned long exynos4x12_get_pll_clk(int pllreg) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + unsigned long r, k = 0; + + switch (pllreg) { + case APLL: + r = readl(&clk->apll_con0); + break; + case MPLL: + r = readl(&clk->mpll_con0); + break; + case EPLL: + r = readl(&clk->epll_con0); + k = readl(&clk->epll_con1); + break; + case VPLL: + r = readl(&clk->vpll_con0); + k = readl(&clk->vpll_con1); + break; + default: + printf("Unsupported PLL (%d)\n", pllreg); + return 0; + } + + return exynos_get_pll_clk(pllreg, r, k); +} + /* exynos5: return pll clock frequency */ static unsigned long exynos5_get_pll_clk(int pllreg) { @@ -181,6 +211,28 @@ static unsigned long exynos4_get_arm_clk(void) return armclk; } +/* exynos4x12: return ARM clock frequency */ +static unsigned long exynos4x12_get_arm_clk(void) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + unsigned long div; + unsigned long armclk; + unsigned int core_ratio; + unsigned int core2_ratio; + + div = readl(&clk->div_cpu0); + + /* CORE_RATIO: [2:0], CORE2_RATIO: [30:28] */ + core_ratio = (div >> 0) & 0x7; + core2_ratio = (div >> 28) & 0x7; + + armclk = get_pll_clk(APLL) / (core_ratio + 1); + armclk /= (core2_ratio + 1); + + return armclk; +} + /* exynos5: return ARM clock frequency */ static unsigned long exynos5_get_arm_clk(void) { @@ -246,6 +298,20 @@ static unsigned long exynos4_get_pwm_clk(void) return pclk; } +/* exynos4x12: return pwm clock frequency */ +static unsigned long exynos4x12_get_pwm_clk(void) +{ + unsigned long pclk, sclk; + unsigned int ratio; + + sclk = get_pll_clk(MPLL); + ratio = 8; + + pclk = sclk / (ratio + 1); + + return pclk; +} + /* exynos5: return pwm clock frequency */ static unsigned long exynos5_get_pwm_clk(void) { @@ -314,6 +380,51 @@ static unsigned long exynos4_get_uart_clk(int dev_index) return uclk; } +/* exynos4x12: return uart clock frequency */ +static unsigned long exynos4x12_get_uart_clk(int dev_index) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + unsigned long uclk, sclk; + unsigned int sel; + unsigned int ratio; + + /* + * CLK_SRC_PERIL0 + * UART0_SEL [3:0] + * UART1_SEL [7:4] + * UART2_SEL [8:11] + * UART3_SEL [12:15] + * UART4_SEL [16:19] + */ + sel = readl(&clk->src_peril0); + sel = (sel >> (dev_index << 2)) & 0xf; + + if (sel == 0x6) + sclk = get_pll_clk(MPLL); + else if (sel == 0x7) + sclk = get_pll_clk(EPLL); + else if (sel == 0x8) + sclk = get_pll_clk(VPLL); + else + return 0; + + /* + * CLK_DIV_PERIL0 + * UART0_RATIO [3:0] + * UART1_RATIO [7:4] + * UART2_RATIO [8:11] + * UART3_RATIO [12:15] + * UART4_RATIO [16:19] + */ + ratio = readl(&clk->div_peril0); + ratio = (ratio >> (dev_index << 2)) & 0xf; + + uclk = sclk / (ratio + 1); + + return uclk; +} + /* exynos5: return uart clock frequency */ static unsigned long exynos5_get_uart_clk(int dev_index) { @@ -388,6 +499,33 @@ static void exynos4_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); } +/* exynos4x12: set the mmc clock */ +static void exynos4x12_set_mmc_clk(int dev_index, unsigned int div) +{ + struct exynos4x12_clock *clk = + (struct exynos4x12_clock *)samsung_get_base_clock(); + unsigned int addr; + unsigned int val; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC1_PRE_RATIO [31:24] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC3_PRE_RATIO [31:24] + */ + if (dev_index < 2) { + addr = (unsigned int)&clk->div_fsys1; + } else { + addr = (unsigned int)&clk->div_fsys2; + dev_index -= 2; + } + + val = readl(addr); + val &= ~(0xff << ((dev_index << 4) + 8)); + val |= (div & 0xff) << ((dev_index << 4) + 8); + writel(val, addr); +} + /* exynos5: set the mmc clock */ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) { @@ -710,16 +848,22 @@ unsigned long get_pll_clk(int pllreg) { if (cpu_is_exynos5()) return exynos5_get_pll_clk(pllreg); - else + else { + if (proid_is_exynos4412()) + return exynos4x12_get_pll_clk(pllreg); return exynos4_get_pll_clk(pllreg); + } } unsigned long get_arm_clk(void) { if (cpu_is_exynos5()) return exynos5_get_arm_clk(); - else + else { + if (proid_is_exynos4412()) + return exynos4x12_get_arm_clk(); return exynos4_get_arm_clk(); + } } unsigned long get_i2c_clk(void) @@ -736,24 +880,33 @@ unsigned long get_pwm_clk(void) { if (cpu_is_exynos5()) return exynos5_get_pwm_clk(); - else + else { + if (proid_is_exynos4412()) + return exynos4x12_get_pwm_clk(); return exynos4_get_pwm_clk(); + } } unsigned long get_uart_clk(int dev_index) { if (cpu_is_exynos5()) return exynos5_get_uart_clk(dev_index); - else + else { + if (proid_is_exynos4412()) + return exynos4x12_get_uart_clk(dev_index); return exynos4_get_uart_clk(dev_index); + } } void set_mmc_clk(int dev_index, unsigned int div) { if (cpu_is_exynos5()) exynos5_set_mmc_clk(dev_index, div); - else + else { + if (proid_is_exynos4412()) + exynos4x12_set_mmc_clk(dev_index, div); exynos4_set_mmc_clk(dev_index, div); + } } unsigned long get_lcd_clk(void)