Patchwork [U-Boot,1/1] ipu common: reset ipuv3 correctly

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Submitter Liu Ying
Date Oct. 6, 2012, 2:16 p.m.
Message ID <1349532964-8480-1-git-send-email-Ying.liu@freescale.com>
Download mbox | patch
Permalink /patch/189755/
State Accepted
Delegated to: Anatolij Gustschin
Headers show

Comments

Liu Ying - Oct. 6, 2012, 2:16 p.m.
From: Liu Ying <Ying.Liu@freescale.com>

This patch checks self-clear sw_ipu_rst bit in
SCR register of SRC controller to be cleared
after setting it to high to reset IPUv3. This
makes sure that IPUv3 finishes sofware reset.
A timeout mechanism is added to stop polling
on the bit status in case the bit could not be
cleared by the hardware automatically within
10 millisecond.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
---
 drivers/video/ipu_common.c |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)
Anatolij Gustschin - Oct. 19, 2012, 11:58 p.m.
Hi,
On Sat, 6 Oct 2012 22:16:04 +0800
Liu Ying <Ying.liu@freescale.com> wrote:

> From: Liu Ying <Ying.Liu@freescale.com>
> 
> This patch checks self-clear sw_ipu_rst bit in
> SCR register of SRC controller to be cleared
> after setting it to high to reset IPUv3. This
> makes sure that IPUv3 finishes sofware reset.
> A timeout mechanism is added to stop polling
> on the bit status in case the bit could not be
> cleared by the hardware automatically within
> 10 millisecond.
> 
> Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
> ---
>  drivers/video/ipu_common.c |   10 ++++++++++
>  1 files changed, 10 insertions(+), 0 deletions(-)

applied, thanks!

Anatolij

Patch

diff --git a/drivers/video/ipu_common.c b/drivers/video/ipu_common.c
index 2020da9..fcc1745 100644
--- a/drivers/video/ipu_common.c
+++ b/drivers/video/ipu_common.c
@@ -94,6 +94,7 @@  struct ipu_ch_param {
 	temp1; \
 })
 
+#define IPU_SW_RST_TOUT_USEC	(10000)
 
 void clk_enable(struct clk *clk)
 {
@@ -392,11 +393,20 @@  void ipu_reset(void)
 {
 	u32 *reg;
 	u32 value;
+	int timeout = IPU_SW_RST_TOUT_USEC;
 
 	reg = (u32 *)SRC_BASE_ADDR;
 	value = __raw_readl(reg);
 	value = value | SW_IPU_RST;
 	__raw_writel(value, reg);
+
+	while (__raw_readl(reg) & SW_IPU_RST) {
+		udelay(1);
+		if (!(timeout--)) {
+			printf("ipu software reset timeout\n");
+			break;
+		}
+	};
 }
 
 /*