From patchwork Sat Oct 6 10:18:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 189675 Return-Path: X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Received: from merlin.infradead.org (merlin.infradead.org [IPv6:2001:4978:20e::2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id A190C2C032F for ; Sat, 6 Oct 2012 20:20:53 +1000 (EST) Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.76 #1 (Red Hat Linux)) id 1TKRSt-00082t-Th; Sat, 06 Oct 2012 10:18:35 +0000 Received: from inca-roads.misterjones.org ([213.251.177.50]) by merlin.infradead.org with esmtps (Exim 4.76 #1 (Red Hat Linux)) id 1TKRSq-00082c-F3 for linux-arm-kernel@lists.infradead.org; Sat, 06 Oct 2012 10:18:33 +0000 Received: from www-data by inca-roads.misterjones.org with local (Exim 4.69) (envelope-from ) id 1TKRSh-0004l2-Fd; Sat, 06 Oct 2012 12:18:23 +0200 To: Tony Lindgren Subject: Re: [PATCH v2 2/7] ARM: virt: allow the kernel to be entered in HYP mode X-PHP-Originating-Script: 0:func.inc MIME-Version: 1.0 Date: Sat, 06 Oct 2012 12:18:23 +0200 From: Marc Zyngier Organization: ARM Ltd In-Reply-To: <20121005200822.GQ3874@atomide.com> References: <1347036934-8519-1-git-send-email-marc.zyngier@arm.com> <1347036934-8519-3-git-send-email-marc.zyngier@arm.com> <20121005200822.GQ3874@atomide.com> Message-ID: <6d3553bfe8a2d1ac88cab852100616a7@localhost> X-Sender: marc.zyngier@arm.com User-Agent: RoundCube Webmail/0.3.1 X-SA-Exim-Connect-IP: X-SA-Exim-Rcpt-To: tony@atomide.com, dave.martin@linaro.org, linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org, nico@fluxnic.net, linux@arm.linux.org.uk X-SA-Exim-Mail-From: marc.zyngier@arm.com X-SA-Exim-Scanned: No (on inca-roads.misterjones.org); SAEximRunCond expanded to false X-Spam-Note: CRM114 invocation failed X-Spam-Score: -1.2 (-) X-Spam-Report: SpamAssassin version 3.3.2 on merlin.infradead.org summary: Content analysis details: (-1.2 points) pts rule name description ---- ---------------------- -------------------------------------------------- 0.7 SPF_SOFTFAIL SPF: sender does not match SPF record (softfail) -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] Cc: Dave Martin , linux-omap@vger.kernel.org, Russell King - ARM Linux , linux-arm-kernel@lists.infradead.org, Nicolas Pitre X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.14 Precedence: list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: linux-arm-kernel-bounces@lists.infradead.org Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org List-Id: linux-imx-kernel.lists.patchwork.ozlabs.org Hi Tony, On Fri, 5 Oct 2012 13:08:22 -0700, Tony Lindgren wrote: > Hi, > > * Marc Zyngier [120907 10:04]: >> From: Dave Martin >> >> This patch does two things: >> >> * Ensure that asynchronous aborts are masked at kernel entry. >> The bootloader should be masking these anyway, but this reduces >> the damage window just in case it doesn't. >> >> * Enter svc mode via exception return to ensure that CPU state is >> properly serialised. This does not matter when switching from >> an ordinary privileged mode ("PL1" modes in ARMv7-AR rev C >> parlance), but it potentially does matter when switching from a >> another privileged mode such as hyp mode. >> >> This should allow the kernel to boot safely either from svc mode or >> hyp mode, even if no support for use of the ARM Virtualization >> Extensions is built into the kernel. >> >> Signed-off-by: Dave Martin >> Signed-off-by: Marc Zyngier > > Just bisected this down in linux-next for breaking booting of > my omap2420 ARMv6 based n8x0.. > >> --- a/arch/arm/kernel/head.S >> +++ b/arch/arm/kernel/head.S >> @@ -83,8 +83,12 @@ ENTRY(stext) >> THUMB( .thumb ) @ switch to Thumb now. >> THUMB(1: ) >> >> - setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode >> - @ and irqs disabled >> +#ifdef CONFIG_ARM_VIRT_EXT >> + bl __hyp_stub_install >> +#endif >> + @ ensure svc mode and all interrupts masked >> + safe_svcmode_maskall r9 >> + >> mrc p15, 0, r9, c0, c0 @ get processor id >> bl __lookup_processor_type @ r5=procinfo r9=cpuid >> movs r10, r5 @ invalid processor (r5=0)? > > ..and looks like undoing this part fixes it. Any ideas? > > I quickly tried disabling ARCH_OMAP3 and ARCH_OMAP4 so it's > ARMv6 but that does not help. If you compiled for v6 only, we can safely exclude __hyp_stub_install, and I assume that you get past the decompressor. If so, that indicates some side effect of the safe_svcmode_maskall macro, and I suspect the "movs pc, lr" bit. Can you try the attached patch? It basically falls back to the previous behaviour if not entered in HYP mode. Thanks, M. Acked-by: Nicolas Pitre Tested-by: Tony Lindgren diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 658a15d..b21b97f 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -254,16 +254,17 @@ mov lr , \reg and lr , lr , #MODE_MASK cmp lr , #HYP_MODE - orr \reg , \reg , #PSR_A_BIT | PSR_I_BIT | PSR_F_BIT + orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT bic \reg , \reg , #MODE_MASK orr \reg , \reg , #SVC_MODE THUMB( orr \reg , \reg , #PSR_T_BIT ) - msr spsr_cxsf, \reg - adr lr, BSYM(2f) bne 1f + orr \reg, \reg, #PSR_A_BIT + adr lr, BSYM(2f) + msr spsr_cxsf, \reg __MSR_ELR_HYP(14) __ERET -1: movs pc, lr +1: msr cpsr_c, \reg 2: .endm