From patchwork Sat Oct 6 00:45:17 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John David Anglin X-Patchwork-Id: 189643 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 76DA72C0180 for ; Sat, 6 Oct 2012 10:45:28 +1000 (EST) Comment: DKIM? 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See http://antispam.yahoo.com/domainkeys DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=default; d=gcc.gnu.org; h=Received:Received:X-SWARE-Spam-Status:X-Spam-Check-By:Received:Received:Date:From:To:Subject:Message-ID:Reply-To:MIME-Version:Content-Type:Content-Disposition:User-Agent:Mailing-List:Precedence:List-Id:List-Unsubscribe:List-Archive:List-Post:List-Help:Sender:Delivered-To; b=NrTlDi8YAJlXPiGvnHDhyvXU00HIk9MHF7/mkqbhw13gorRZ/1Jokuyj1xFlXy iwLfWxok2woPBjg+2I6Dx70FQjzXaIDHTwUeNKgaL7+eq6wMFHAj8wgVlPB9ycTE dFguwpSI3h34HLD5GzOxwEqn/NGvHXEJLW334tVb/Qug4=; Received: (qmail 1245 invoked by alias); 6 Oct 2012 00:45:25 -0000 Received: (qmail 1226 invoked by uid 22791); 6 Oct 2012 00:45:24 -0000 X-SWARE-Spam-Status: No, hits=-3.0 required=5.0 tests=AWL, BAYES_00, RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from hiauly1.hia.nrc.ca (HELO hiauly1.hia.nrc.ca) (132.246.10.84) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Sat, 06 Oct 2012 00:45:19 +0000 Received: by hiauly1.hia.nrc.ca (Postfix, from userid 1000) id 9143E4E89; Fri, 5 Oct 2012 20:45:18 -0400 (EDT) Date: Fri, 5 Oct 2012 20:45:17 -0400 From: John David Anglin To: gcc-patches@gcc.gnu.org Subject: [committed] Remove 32-bit PA DImode and, not and, ior and xor patterns Message-ID: <20121006004517.GA12695@hiauly1.hia.nrc.ca> Reply-To: John David Anglin MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.16 (2007-06-09) Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org The 32-bit DImode patterns for and and friends are not split on parisc. Based on inspection of the assembly code generated for gcc.dg/lower-subreg-1.c, it better if we let lower subreg split the DImode objects on parisc and remove the current DImode patterns. Tested on hppa-unknown-linux-gnu and committed to trunk. Dave Index: config/pa/pa.md =================================================================== --- config/pa/pa.md (revision 191943) +++ config/pa/pa.md (working copy) @@ -5621,24 +5621,10 @@ [(set (match_operand:DI 0 "register_operand" "") (and:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "and_operand" "")))] - "" - " -{ - /* Both operands must be register operands. */ - if (!TARGET_64BIT && !register_operand (operands[2], DImode)) - FAIL; -}") + "TARGET_64BIT" + "") (define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "register_operand" "r")))] - "!TARGET_64BIT" - "and %1,%2,%0\;and %R1,%R2,%R0" - [(set_attr "type" "binary") - (set_attr "length" "8")]) - -(define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (and:DI (match_operand:DI 1 "register_operand" "%?r,0") (match_operand:DI 2 "and_operand" "rO,P")))] @@ -5662,15 +5648,6 @@ [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (not:DI (match_operand:DI 1 "register_operand" "r")) (match_operand:DI 2 "register_operand" "r")))] - "!TARGET_64BIT" - "andcm %2,%1,%0\;andcm %R2,%R1,%R0" - [(set_attr "type" "binary") - (set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (and:DI (not:DI (match_operand:DI 1 "register_operand" "r")) - (match_operand:DI 2 "register_operand" "r")))] "TARGET_64BIT" "andcm %2,%1,%0" [(set_attr "type" "binary") @@ -5689,24 +5666,10 @@ [(set (match_operand:DI 0 "register_operand" "") (ior:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "reg_or_cint_ior_operand" "")))] - "" - " -{ - /* Both operands must be register operands. */ - if (!TARGET_64BIT && !register_operand (operands[2], DImode)) - FAIL; -}") + "TARGET_64BIT" + "") (define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (ior:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "register_operand" "r")))] - "!TARGET_64BIT" - "or %1,%2,%0\;or %R1,%R2,%R0" - [(set_attr "type" "binary") - (set_attr "length" "8")]) - -(define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,r") (ior:DI (match_operand:DI 1 "register_operand" "0,0") (match_operand:DI 2 "cint_ior_operand" "M,i")))] @@ -5754,24 +5717,13 @@ [(set (match_operand:DI 0 "register_operand" "") (xor:DI (match_operand:DI 1 "register_operand" "") (match_operand:DI 2 "register_operand" "")))] - "" - " -{ -}") + "TARGET_64BIT" + "") (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") (xor:DI (match_operand:DI 1 "register_operand" "%r") (match_operand:DI 2 "register_operand" "r")))] - "!TARGET_64BIT" - "xor %1,%2,%0\;xor %R1,%R2,%R0" - [(set_attr "type" "binary") - (set_attr "length" "8")]) - -(define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r") - (xor:DI (match_operand:DI 1 "register_operand" "%r") - (match_operand:DI 2 "register_operand" "r")))] "TARGET_64BIT" "xor %1,%2,%0" [(set_attr "type" "binary")