From patchwork Fri Oct 5 23:55:00 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 189633 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 24E4D2C031D for ; Sat, 6 Oct 2012 10:19:05 +1000 (EST) Received: from localhost ([::1]:41540 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TKHlA-0001D2-Lc for incoming@patchwork.ozlabs.org; Fri, 05 Oct 2012 19:56:48 -0400 Received: from eggs.gnu.org ([208.118.235.92]:42642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TKHju-0007Lw-R8 for qemu-devel@nongnu.org; Fri, 05 Oct 2012 19:55:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TKHjt-0003Wp-IF for qemu-devel@nongnu.org; Fri, 05 Oct 2012 19:55:30 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:51027) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TKHjt-0003Qe-6u for qemu-devel@nongnu.org; Fri, 05 Oct 2012 19:55:29 -0400 Received: by mail-pb0-f45.google.com with SMTP id rp2so2425542pbb.4 for ; Fri, 05 Oct 2012 16:55:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:from:to:cc:subject:date:message-id:x-mailer:in-reply-to :references; bh=kyanxgM/GefuwjqKnDfJj0V1XUpg9P28DqzqdXNKK/U=; b=hPnsd4puB4B0PenHTLyWPx0NgSAPLP9C+O/W6zn47KIHYRAcn1FsgOv09SqReKPd0j xv3YKEeZBWSM4zkCAbBnxsXzUhTpX6DknYcQ9mRo0DLh0MZW7aw+4/L9YSn7+syiF39u d4j82sNriKoABrs/Ogcqfbw+Fn7wXgVid/SKHprn2qq+5HZSXmjxHZjDVqvrdBYnds52 Iabnm6LGxzE9fJBBdzSR2YSR3KU5Mlij4tpXsQ/YYoAAIi2xjnqV0ak+LnI6XvN9sxbL Umlgmm4bREzGpkCRleMnLtkKhFMEzixcBwQkuQD6DQLtbwsjP5fcyuQsOWvRg4a7Fx45 YB+g== Received: by 10.68.230.232 with SMTP id tb8mr34717337pbc.19.1349481328786; Fri, 05 Oct 2012 16:55:28 -0700 (PDT) Received: from anchor.twiddle.home (50-194-63-110-static.hfc.comcastbusiness.net. [50.194.63.110]) by mx.google.com with ESMTPS id tw5sm6751873pbc.48.2012.10.05.16.55.27 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 05 Oct 2012 16:55:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 5 Oct 2012 16:55:00 -0700 Message-Id: <1349481310-9237-14-git-send-email-rth@twiddle.net> X-Mailer: git-send-email 1.7.11.4 In-Reply-To: <1349481310-9237-1-git-send-email-rth@twiddle.net> References: <1349481310-9237-1-git-send-email-rth@twiddle.net> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.160.45 Cc: Blue Swirl Subject: [Qemu-devel] [PATCH 13/23] target-sparc: Use DisasCompare and movcond in MOVCC X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Signed-off-by: Richard Henderson --- target-sparc/translate.c | 44 ++++++++++++++++++++------------------------ 1 file changed, 20 insertions(+), 24 deletions(-) diff --git a/target-sparc/translate.c b/target-sparc/translate.c index a7cd677..6c9be29 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -4075,38 +4075,34 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) { int cc = GET_FIELD_SP(insn, 11, 12); int cond = GET_FIELD_SP(insn, 14, 17); - TCGv r_cond; - int l1; + DisasCompare cmp; - r_cond = tcg_temp_new(); if (insn & (1 << 18)) { - if (cc == 0) - gen_cond(r_cond, 0, cond, dc); - else if (cc == 2) - gen_cond(r_cond, 1, cond, dc); - else + if (cc == 0) { + gen_compare(&cmp, 0, cond, dc); + } else if (cc == 2) { + gen_compare(&cmp, 1, cond, dc); + } else { goto illegal_insn; + } } else { - gen_fcond(r_cond, cc, cond); + gen_fcompare(&cmp, cc, cond); } - l1 = gen_new_label(); - - tcg_gen_brcondi_tl(TCG_COND_EQ, r_cond, 0, l1); - if (IS_IMM) { /* immediate */ - TCGv r_const; - + /* The get_src2 above loaded the normal 13-bit + immediate field, not the 11-bit field we have + in movcc. But it did handle the reg case. */ + if (IS_IMM) { simm = GET_FIELD_SPs(insn, 0, 10); - r_const = tcg_const_tl(simm); - gen_movl_TN_reg(rd, r_const); - tcg_temp_free(r_const); - } else { - rs2 = GET_FIELD_SP(insn, 0, 4); - gen_movl_reg_TN(rs2, cpu_tmp0); - gen_movl_TN_reg(rd, cpu_tmp0); + tcg_gen_movi_tl(cpu_src2, simm); } - gen_set_label(l1); - tcg_temp_free(r_cond); + + gen_movl_reg_TN(rd, cpu_dst); + tcg_gen_movcond_tl(cmp.cond, cpu_dst, + cmp.c1, cmp.c2, + cpu_src2, cpu_dst); + free_compare(&cmp); + gen_movl_TN_reg(rd, cpu_dst); break; } case 0x2d: /* V9 sdivx */