From patchwork Fri Oct 5 12:58:52 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 189475 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id CB3352C00BF for ; Fri, 5 Oct 2012 22:59:47 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id C0D1C280E6; Fri, 5 Oct 2012 14:59:28 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id htZlckbX+cQd; Fri, 5 Oct 2012 14:59:28 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 201C4280B4; Fri, 5 Oct 2012 14:59:11 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 80D2B2808D for ; Fri, 5 Oct 2012 14:59:01 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id VZylwCCiCJ8W for ; Fri, 5 Oct 2012 14:59:00 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-we0-f172.google.com (mail-we0-f172.google.com [74.125.82.172]) by theia.denx.de (Postfix) with ESMTPS id 993F72808C for ; Fri, 5 Oct 2012 14:58:58 +0200 (CEST) Received: by mail-we0-f172.google.com with SMTP id u46so1035549wey.3 for ; Fri, 05 Oct 2012 05:58:58 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=eeeK6BKLUw8/jqiYfbAk5TuFixklINwJ0SVGfIDYrto=; b=X9V1DNkuDxAO9uj9ntMOr3QGy36uzI378JOaqbVP2JvBhWOLCTz0wmutAGtrf9oJfY 8947odfG3InHwV/pEC+yGh2vj6HeJD9INGyTYnjILhK8MqWLj11009Ux21T3fqO0QnB2 JriMRWC3Bv8dLLUQvHVcsvk2AV8a6tsCcjZoLPK7dPB8nk7k4/3grD33UGxFqe0G8aLY 5UAgxBGTuocQ7SxGGTujNnCjsA+J7iXM4xxEVci7MWYjm853JqZNagsU1tDOZvFfmX3+ O7kfg7X+fkUkcrag5Xa0W9+IViDc2hPTHQQVCMwfiYZjikzlq4WpuLHJtlJhyckFWqvV eNzA== Received: by 10.180.107.163 with SMTP id hd3mr3246638wib.19.1349441938078; Fri, 05 Oct 2012 05:58:58 -0700 (PDT) Received: from localhost (nat-2.starnet.cz. [92.62.224.2]) by mx.google.com with ESMTPS id bn7sm2552439wib.8.2012.10.05.05.58.57 (version=TLSv1/SSLv3 cipher=OTHER); Fri, 05 Oct 2012 05:58:57 -0700 (PDT) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 5 Oct 2012 14:58:52 +0200 Message-Id: <1349441933-22840-3-git-send-email-monstr@monstr.eu> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1349441933-22840-1-git-send-email-monstr@monstr.eu> References: <1349441933-22840-1-git-send-email-monstr@monstr.eu> X-Gm-Message-State: ALoCoQntcz0yOxcqPxumNei0Yzy8mVG6K0jBXCTR5DKQE/IDs2ecyixOsi5sy+5lv0KeKFSU2Q1R Subject: [U-Boot] [PATCH 3/4] microblaze: Flush caches before enabling them X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Flushing caches is necessary because of soft reset which doesn't clear caches. Signed-off-by: Michal Simek Reviewed-by: Marek Vasut --- arch/microblaze/cpu/cache.c | 5 ----- arch/microblaze/cpu/start.S | 6 ++++++ arch/microblaze/lib/bootm.c | 5 ----- include/configs/microblaze-generic.h | 4 ++++ 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/microblaze/cpu/cache.c b/arch/microblaze/cpu/cache.c index d258a69..ce066b9 100644 --- a/arch/microblaze/cpu/cache.c +++ b/arch/microblaze/cpu/cache.c @@ -61,12 +61,7 @@ void dcache_enable (void) { void dcache_disable(void) { #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif MSRCLR(0x80); } diff --git a/arch/microblaze/cpu/start.S b/arch/microblaze/cpu/start.S index 8564c4e..3da711d 100644 --- a/arch/microblaze/cpu/start.S +++ b/arch/microblaze/cpu/start.S @@ -132,6 +132,12 @@ _start: rsubi r8, r10, 0x26 sh r6, r0, r8 + /* Flush cache before enable cache */ + addik r5, r0, 0 + addik r6, r0, XILINX_DCACHE_BYTE_SIZE +flush: bralid r15, flush_cache + nop + /* enable instruction and data cache */ mfs r12, rmsr ori r12, r12, 0xa0 diff --git a/arch/microblaze/lib/bootm.c b/arch/microblaze/lib/bootm.c index 95cee50..66d21f4 100644 --- a/arch/microblaze/lib/bootm.c +++ b/arch/microblaze/lib/bootm.c @@ -70,12 +70,7 @@ int do_bootm_linux(int flag, int argc, char * const argv[], bootm_headers_t *ima #endif #ifdef XILINX_USE_DCACHE -#ifdef XILINX_DCACHE_BYTE_SIZE flush_cache(0, XILINX_DCACHE_BYTE_SIZE); -#else -#warning please rebuild BSPs and update configuration - flush_cache(0, 32768); -#endif #endif /* * Linux Kernel Parameters (passing device tree): diff --git a/include/configs/microblaze-generic.h b/include/configs/microblaze-generic.h index 721cd90..eed38c1 100644 --- a/include/configs/microblaze-generic.h +++ b/include/configs/microblaze-generic.h @@ -287,6 +287,10 @@ # undef CONFIG_DCACHE #endif +#ifndef XILINX_DCACHE_BYTE_SIZE +#define XILINX_DCACHE_BYTE_SIZE 32768 +#endif + /* * BOOTP options */