Patchwork [U-Boot,07/11] arm: ks8695/cm4008/cm41xx: Parameterize SDRAM

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Submitter Yann Vernier
Date Oct. 5, 2012, 12:09 p.m.
Message ID <1349438998-10954-8-git-send-email-yann.vernier@orsoc.se>
Download mbox | patch
Permalink /patch/189469/
State Changes Requested
Delegated to: Albert ARIBAUD
Headers show

Comments

Yann Vernier - Oct. 5, 2012, 12:09 p.m.
Allows configuration macros to set SDRAM parameters.
---
 arch/arm/cpu/arm920t/ks8695/lowlevel_init.S |   20 +++++++++++---------
 1 file changed, 11 insertions(+), 9 deletions(-)
Albert ARIBAUD - Oct. 18, 2012, 7:11 p.m.
Hi Yann,

On Fri,  5 Oct 2012 14:09:54 +0200, Yann Vernier
<yann.vernier@orsoc.se> wrote:

> Allows configuration macros to set SDRAM parameters.
> ---
>  arch/arm/cpu/arm920t/ks8695/lowlevel_init.S |   20 +++++++++++---------
>  1 file changed, 11 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
> index 74579ed..bec9738 100644
> --- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
> +++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
> @@ -157,19 +157,20 @@ highflash:
>  	/*
>  	 * before relocating, we have to setup RAM timing
>  	 */
> +#if CONFIG_SYS_SDCS0_PARAMS

That seems a newly introduced macro, which only pertains to certain
hardwares but does not entirely show it in the name, i.e. readers may
wrongly conclude that any board could define CONFIG_SYS_SDCS0_PARAMS.
Rename the macro to also show which SoC it refers to.

>  	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
> -#if (PHYS_SDRAM_1_SIZE == 0x02000000)
> -	ldr	r2, =0x7fc0000e		/* 32MB */
> -#else
> -	ldr	r2, =0x3fc0000e		/* 16MB */
> -#endif
> +	ldr	r2, =CONFIG_KS8695_SDCON0_VALUE
>  	str	r2, [r1]		/* configure sdram bank0 setup */
> +#endif
> +#if CONFIG_SYS_SDCS1_PARAMS
>  	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
> -	mov	r2, #0
> +	mov	r2, #CONFIG_KS8695_SDCON1_VALUE
>  	str	r2, [r1]		/* configure sdram bank1 setup */
> +#endif
>  
> +#if CONFIG_SYS_SDCS0_PARAMS || CONFIG_SYS_SDCS1_PARAMS
>  	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
> -	ldr	r2, =0x0000000a
> +	ldr	r2, =CONFIG_KS8695_SDGCON_VALUE
>  	str	r2, [r1]		/* set RAS/CAS timing */
>  
>  	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
> @@ -184,15 +185,16 @@ highflash:
>  	ldr	r2, =0x00000020
>  	str	r2, [r1]		/* set for fast refresh */
>  	DELAY_FOR 0x100, r0
> -	ldr	r2, =0x00000190
> +	ldr	r2, =CONFIG_SYS_SDRAM_REFRESH_RATE
>  	str	r2, [r1]		/* set normal refresh timing */
>  
>  	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
> -	ldr	r2, =0x00020033
> +	ldr	r2, =(0x00020000 | CONFIG_SYS_SDRAM_MODE)
>  	str	r2, [r1]		/* send mode command */
>  	DELAY_FOR 0x100, r0
>  	ldr	r2, =0x01f00000
>  	str	r2, [r1]		/* enable sdram fifos */
> +#endif
>  
>  	/*
>  	 * set pll to top speed



Amicalement,

Patch

diff --git a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
index 74579ed..bec9738 100644
--- a/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
+++ b/arch/arm/cpu/arm920t/ks8695/lowlevel_init.S
@@ -157,19 +157,20 @@  highflash:
 	/*
 	 * before relocating, we have to setup RAM timing
 	 */
+#if CONFIG_SYS_SDCS0_PARAMS
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL0)
-#if (PHYS_SDRAM_1_SIZE == 0x02000000)
-	ldr	r2, =0x7fc0000e		/* 32MB */
-#else
-	ldr	r2, =0x3fc0000e		/* 16MB */
-#endif
+	ldr	r2, =CONFIG_KS8695_SDCON0_VALUE
 	str	r2, [r1]		/* configure sdram bank0 setup */
+#endif
+#if CONFIG_SYS_SDCS1_PARAMS
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_CTRL1)
-	mov	r2, #0
+	mov	r2, #CONFIG_KS8695_SDCON1_VALUE
 	str	r2, [r1]		/* configure sdram bank1 setup */
+#endif
 
+#if CONFIG_SYS_SDCS0_PARAMS || CONFIG_SYS_SDCS1_PARAMS
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_GENERAL)
-	ldr	r2, =0x0000000a
+	ldr	r2, =CONFIG_KS8695_SDGCON_VALUE
 	str	r2, [r1]		/* set RAS/CAS timing */
 
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
@@ -184,15 +185,16 @@  highflash:
 	ldr	r2, =0x00000020
 	str	r2, [r1]		/* set for fast refresh */
 	DELAY_FOR 0x100, r0
-	ldr	r2, =0x00000190
+	ldr	r2, =CONFIG_SYS_SDRAM_REFRESH_RATE
 	str	r2, [r1]		/* set normal refresh timing */
 
 	ldr	r1, =(KS8695_IO_BASE+KS8695_SDRAM_BUFFER)
-	ldr	r2, =0x00020033
+	ldr	r2, =(0x00020000 | CONFIG_SYS_SDRAM_MODE)
 	str	r2, [r1]		/* send mode command */
 	DELAY_FOR 0x100, r0
 	ldr	r2, =0x01f00000
 	str	r2, [r1]		/* enable sdram fifos */
+#endif
 
 	/*
 	 * set pll to top speed