Patchwork [U-Boot] MPC85xx: remove support for TQM85xx boards

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Submitter Wolfgang Denk
Date Oct. 4, 2012, 9:36 a.m.
Message ID <1349343378-12115-1-git-send-email-wd@denx.de>
Download mbox | patch
Permalink /patch/189079/
State Accepted
Delegated to: Tom Rini
Headers show

Comments

Wolfgang Denk - Oct. 4, 2012, 9:36 a.m.
Due to grown code sizes the TQM85xx boards don't build any more with
some older tool chains (like ELDK 4.2).  As these boards have long
reached EOL it seems a waste of effort trying to fix them.  The vendor
has agreed to drop support for them, too.  So let's get rid of them.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Stefan Roese <sr@denx.de>
cc: Kim Phillips <kim.phillips@freescale.com>
---
 MAINTAINERS                 |   2 -
 board/tqc/tqm85xx/Makefile  |  50 ----
 board/tqc/tqm85xx/law.c     |  79 -----
 board/tqc/tqm85xx/nand.c    | 472 ------------------------------
 board/tqc/tqm85xx/sdram.c   | 436 ---------------------------
 board/tqc/tqm85xx/tlb.c     | 214 --------------
 board/tqc/tqm85xx/tqm85xx.c | 626 ---------------------------------------
 boards.cfg                  |   7 -
 doc/README.scrapyard        |   5 +-
 drivers/mtd/nand/fsl_upm.c  |  10 +-
 include/configs/TQM85xx.h   | 697 --------------------------------------------
 11 files changed, 8 insertions(+), 2590 deletions(-)
 delete mode 100644 board/tqc/tqm85xx/Makefile
 delete mode 100644 board/tqc/tqm85xx/law.c
 delete mode 100644 board/tqc/tqm85xx/nand.c
 delete mode 100644 board/tqc/tqm85xx/sdram.c
 delete mode 100644 board/tqc/tqm85xx/tlb.c
 delete mode 100644 board/tqc/tqm85xx/tqm85xx.c
 delete mode 100644 include/configs/TQM85xx.h
Stefan Roese - Oct. 4, 2012, 9:40 a.m.
On 10/04/2012 11:36 AM, Wolfgang Denk wrote:
> Due to grown code sizes the TQM85xx boards don't build any more with
> some older tool chains (like ELDK 4.2).  As these boards have long
> reached EOL it seems a waste of effort trying to fix them.  The vendor
> has agreed to drop support for them, too.  So let's get rid of them.
> 
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> cc: Kim Phillips <kim.phillips@freescale.com>

Acked-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan
Tom Rini - Oct. 4, 2012, 10:02 p.m.
On Thu, Oct 04, 2012 at 11:36:18AM +0200, Wolfgang Denk wrote:

> Due to grown code sizes the TQM85xx boards don't build any more with
> some older tool chains (like ELDK 4.2).  As these boards have long
> reached EOL it seems a waste of effort trying to fix them.  The vendor
> has agreed to drop support for them, too.  So let's get rid of them.
> 
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> cc: Kim Phillips <kim.phillips@freescale.com>

To be consistent, I've asked for v2012.10 to be the last stop for
various platforms.   Given that it doesn't build however, and the
maintainer doesn't want to fix the build problem, I'm going to remove
them.  I think that's consistent still.
Tom Rini - Oct. 5, 2012, 10:26 p.m.
On Thu, Oct 04, 2012 at 11:36:18AM +0200, Wolfgang Denk wrote:

> Due to grown code sizes the TQM85xx boards don't build any more with
> some older tool chains (like ELDK 4.2).  As these boards have long
> reached EOL it seems a waste of effort trying to fix them.  The vendor
> has agreed to drop support for them, too.  So let's get rid of them.
> 
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Stefan Roese <sr@denx.de>
> cc: Kim Phillips <kim.phillips@freescale.com>

Applied to u-boot/master, thanks!

Patch

diff --git a/MAINTAINERS b/MAINTAINERS
index 54ee1e6..4e3335b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -397,8 +397,6 @@  Stefan Roese <sr@denx.de>
 
 	uc100		MPC857
 
-	TQM85xx		MPC8540/8541/8555/8560
-
 	acadia		PPC405EZ
 	alpr		PPC440GX
 	bamboo		PPC440EP
diff --git a/board/tqc/tqm85xx/Makefile b/board/tqc/tqm85xx/Makefile
deleted file mode 100644
index 0a5501f..0000000
--- a/board/tqc/tqm85xx/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@ 
-#
-# (C) Copyright 2001-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).o
-
-COBJS-y	+= $(BOARD).o
-COBJS-y	+= sdram.o
-COBJS-y	+= law.o
-COBJS-y	+= tlb.o
-
-COBJS-$(CONFIG_NAND) += nand.o
-
-COBJS	:= $(COBJS-y)
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
-	$(call cmd_link_o_target, $(OBJS))
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
deleted file mode 100644
index c596303..0000000
--- a/board/tqc/tqm85xx/law.c
+++ /dev/null
@@ -1,79 +0,0 @@ 
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/fsl_law.h>
-#include <asm/mmu.h>
-
-/*
- * LAW(Local Access Window) configuration:
- *
- * Standard mapping:
- *
- * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
- * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
- * 0xc000_0000	   0xdfff_ffff	   RapidIO or PCI express  512M
- * 0xe000_0000	   0xe000_ffff	   CCSR			   1M
- * 0xe200_0000	   0xe2ff_ffff	   PCI1 IO		   16M
- * 0xe300_0000	   0xe3ff_ffff	   CAN and NAND Flash	   16M
- * 0xef00_0000	   0xefff_ffff     PCI express IO          16M
- * 0xfc00_0000	   0xffff_ffff	   FLASH (boot bank)	   128M
- *
- * Big FLASH mapping:
- *
- * 0x0000_0000	   0x7fff_ffff	   DDR			   2G
- * 0x8000_0000	   0x9fff_ffff	   PCI1 MEM		   512M
- * 0xa000_0000	   0xa000_ffff	   CCSR			   1M
- * 0xa200_0000	   0xa2ff_ffff	   PCI1 IO		   16M
- * 0xa300_0000	   0xa3ff_ffff	   CAN and NAND Flash	   16M
- * 0xaf00_0000	   0xafff_ffff     PCI express IO          16M
- * 0xb000_0000	   0xbfff_ffff	   RapidIO or PCI express  256M
- * 0xc000_0000	   0xffff_ffff	   FLASH (boot bank)	   1G
- *
- * Notes:
- *    CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- *    If flash is 8M at default position (last 8M), no LAW needed.
- */
-
-#ifdef CONFIG_TQM_BIGFLASH
-#define LAW_3_SIZE LAW_SIZE_1G
-#define LAW_5_SIZE LAW_SIZE_256M
-#else
-#define LAW_3_SIZE LAW_SIZE_128M
-#define LAW_5_SIZE LAW_SIZE_512M
-#endif
-
-struct law_entry law_table[] = {
-	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_2G, LAW_TRGT_IF_DDR),
-	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
-#ifndef CONFIG_PCIE1
-	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
-#endif /* CONFIG_PCIE1 */
-#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
-	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
-#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
-};
-
-int num_law_entries = ARRAY_SIZE (law_table);
diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
deleted file mode 100644
index 4b16c31..0000000
--- a/board/tqc/tqm85xx/nand.c
+++ /dev/null
@@ -1,472 +0,0 @@ 
-/*
- * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
- *
- * (C) Copyright 2006
- * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-#include <asm/io.h>
-#include <asm/errno.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/fsl_upm.h>
-#include <ioports.h>
-
-#include <nand.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern uint get_lbc_clock (void);
-
-/* index of UPM RAM array run pattern for NAND command cycle */
-#define	CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS	0x08
-
-/* index of UPM RAM array run pattern for NAND address cycle */
-#define	CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x10
-
-/* Structure for table with supported UPM timings */
-struct upm_freq {
-	ulong freq;
-	const u32 *upm_patt;
-	uchar gpl4_disable;
-	uchar ehtr;
-	uchar ead;
-};
-
-/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */
-
-/* UPM pattern for bus clock = 25 MHz */
-static const u32 upm_patt_25[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00,
-	/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 33.3 MHz */
-static const u32 upm_patt_33[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
-	/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 41.7 MHz */
-static const u32 upm_patt_42[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00,
-	/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 50 MHz */
-static const u32 upm_patt_50[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00,
-	/* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 66.7 MHz */
-static const u32 upm_patt_67[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
-	/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 83.3 MHz */
-static const u32 upm_patt_83[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000,
-	/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 100 MHz */
-static const u32 upm_patt_100[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000,
-	/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 133.3 MHz */
-static const u32 upm_patt_133[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000,
-	/* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* UPM pattern for bus clock = 166.7 MHz */
-static const u32 upm_patt_167[] = {
-	/* Offset */ /* UPM Read Single RAM array entry -> NAND Read Data */
-	/* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300,
-	/* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write CMD */
-	/* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35,
-	/* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Read Burst RAM array entry -> NAND Write ADDR */
-	/* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35,
-	/* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Single RAM array entry -> NAND Write Data */
-	/* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05,
-	/* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-
-	/* UPM Write Burst RAM array entry -> unused */
-	/* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Refresh Timer RAM array entry -> unused */
-	/* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
-	/* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-
-	/* UPM Exception RAM array entry -> unsused */
-	/* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
-};
-
-/* Supported UPM timings */
-struct upm_freq upm_freq_table[] = {
-	/* nominal freq. | ptr to table | GPL4 dis. | EHTR  | EAD */
-	{25000000, upm_patt_25, 1, 0, 0},
-	{33333333, upm_patt_33, 1, 0, 0},
-	{41666666, upm_patt_42, 1, 0, 0},
-	{50000000, upm_patt_50, 0, 0, 0},
-	{66666666, upm_patt_67, 0, 0, 0},
-	{83333333, upm_patt_83, 0, 0, 0},
-	{100000000, upm_patt_100, 0, 1, 1},
-	{133333333, upm_patt_133, 0, 1, 1},
-	{166666666, upm_patt_167, 0, 1, 1},
-};
-
-#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq))
-
-volatile const u32 *nand_upm_patt;
-
-/*
- * write into UPMB ram
- */
-static void upmb_write (u_char addr, ulong val)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	out_be32 (&lbc->mdr, val);
-
-	clrsetbits_be32(&lbc->mbmr, MxMR_MAD_MSK,
-			MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
-
-	/* dummy access to perform write */
-	out_8 ((void __iomem *)CONFIG_SYS_NAND_BASE, 0);
-
-	clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
-}
-
-/*
- * Initialize UPM for NAND flash access.
- */
-static void nand_upm_setup (volatile fsl_lbc_t *lbc)
-{
-	uint i, j;
-	uint or3 = CONFIG_SYS_OR3_PRELIM;
-	uint clock = get_lbc_clock ();
-
-	set_lbc_br(3, 0);	/* disable bank and reset all bits */
-	set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
-
-	/*
-	 * Search appropriate UPM table for bus clock.
-	 * If the bus clock exceeds a tolerated value, take the UPM timing for
-	 * the next higher supported frequency to ensure that access works
-	 * (even the access may be slower then).
-	 */
-	for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++)
-		;
-
-	if (i >= UPM_FREQS)
-	/* no valid entry found */
-		/* take last entry with configuration for max. bus clock */
-		i--;
-
-	if (upm_freq_table[i].ehtr) {
-		/* EHTR must be set due to TQM8548 timing specification */
-		or3 |= OR_UPM_EHTR;
-	}
-	if (upm_freq_table[i].ead)
-		/* EAD must be set due to TQM8548 timing specification */
-		or3 |= OR_UPM_EAD;
-
-	set_lbc_or(3, or3);
-
-	/* Assign address of table */
-	nand_upm_patt = upm_freq_table[i].upm_patt;
-
-	for (j = 0; j < 64; j++) {
-		upmb_write (j, *nand_upm_patt);
-		nand_upm_patt++;
-	}
-
-	/* Put UPM back to normal operation mode */
-	if (upm_freq_table[i].gpl4_disable)
-		/* GPL4 must be disabled according to timing specification */
-		out_be32 (&lbc->mbmr, MxMR_OP_NORM | MxMR_GPL_x4DIS);
-
-	return;
-}
-
-static struct fsl_upm_nand fun = {
-	.width = 8,
-	.upm_cmd_offset = 0x08,
-	.upm_addr_offset = 0x10,
-	.upm_mar_chip_offset = CONFIG_SYS_NAND_CS_DIST,
-	.chip_offset = CONFIG_SYS_NAND_CS_DIST,
-	.chip_delay = NAND_BIG_DELAY_US,
-	.wait_flags = FSL_UPM_WAIT_RUN_PATTERN | FSL_UPM_WAIT_WRITE_BUFFER,
-};
-
-void board_nand_select_device (struct nand_chip *nand, int chip)
-{
-}
-
-int board_nand_init (struct nand_chip *nand)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	if (!nand_upm_patt)
-		nand_upm_setup (lbc);
-
-	fun.upm.io_addr = nand->IO_ADDR_R;
-	fun.upm.mxmr = (void __iomem *)&lbc->mbmr;
-	fun.upm.mdr = (void __iomem *)&lbc->mdr;
-	fun.upm.mar = (void __iomem *)&lbc->mar;
-
-	return fsl_upm_nand_init (nand, &fun);
-}
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
deleted file mode 100644
index baf073e..0000000
--- a/board/tqc/tqm85xx/sdram.c
+++ /dev/null
@@ -1,436 +0,0 @@ 
-
-/*
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/processor.h>
-#include <asm/mmu.h>
-
-struct sdram_conf_s {
-	unsigned long size;
-	unsigned long reg;
-#ifdef CONFIG_TQM8548
-	unsigned long refresh;
-#endif /* CONFIG_TQM8548 */
-};
-
-typedef struct sdram_conf_s sdram_conf_t;
-
-#ifdef CONFIG_TQM8548
-#ifdef CONFIG_TQM8548_AG
-sdram_conf_t ddr_cs_conf[] = {
-	{(1024 << 20), 0x80044202, 0x0002D000},	/* 1024MB, 14x10(4)	*/
-	{ (512 << 20), 0x80044102, 0x0001A000},	/*  512MB, 13x10(4)	*/
-	{ (256 << 20), 0x80040102, 0x00014000},	/*  256MB, 13x10(4)	*/
-	{ (128 << 20), 0x80040101, 0x0000C000},	/*  128MB, 13x9(4)	*/
-};
-#else /* !CONFIG_TQM8548_AG */
-sdram_conf_t ddr_cs_conf[] = {
-	{(512 << 20), 0x80044102, 0x0001A000},	/* 512MB, 13x10(4)	*/
-	{(256 << 20), 0x80040102, 0x00014000},	/* 256MB, 13x10(4)	*/
-	{(128 << 20), 0x80040101, 0x0000C000},	/* 128MB, 13x9(4)	*/
-};
-#endif /* CONFIG_TQM8548_AG */
-#else /* !CONFIG_TQM8548 */
-sdram_conf_t ddr_cs_conf[] = {
-	{(512 << 20), 0x80000202},	/* 512MB, 14x10(4)	*/
-	{(256 << 20), 0x80000102},	/* 256MB, 13x10(4)	*/
-	{(128 << 20), 0x80000101},	/* 128MB, 13x9(4)	*/
-	{( 64 << 20), 0x80000001},	/*  64MB, 12x9(4)	*/
-};
-#endif /* CONFIG_TQM8548 */
-
-#define	N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
-
-int cas_latency (void);
-static phys_size_t sdram_setup(int);
-
-/*
- * Autodetect onboard DDR SDRAM on 85xx platforms
- *
- * NOTE: Some of the hardcoded values are hardware dependant,
- *       so this should be extended for other future boards
- *       using this routine!
- */
-phys_size_t fixed_sdram(void)
-{
-	int casl = 0;
-	phys_size_t dram_size = 0;
-
-	casl = cas_latency();
-	dram_size = sdram_setup(casl);
-	if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) {
-		/*
-		 * Try again with default CAS latency
-		 */
-		printf("Problem with CAS lantency, using default CL %d/10!\n",
-		       CONFIG_DDR_DEFAULT_CL);
-		dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL);
-		puts("       ");
-	}
-	return dram_size;
-}
-
-static phys_size_t sdram_setup(int casl)
-{
-	int i;
-	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-#ifdef CONFIG_TQM8548
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
-	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
-#endif
-#else /* !CONFIG_TQM8548 */
-	unsigned long cfg_ddr_timing1;
-	unsigned long cfg_ddr_mode;
-#endif /* CONFIG_TQM8548 */
-
-	/*
-	 * Disable memory controller.
-	 */
-	ddr->cs0_config = 0;
-	ddr->sdram_cfg = 0;
-
-#ifdef CONFIG_TQM8548
-	/* Timing and refresh settings for DDR2-533 and below */
-
-	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
-	ddr->cs0_config = ddr_cs_conf[0].reg;
-	ddr->timing_cfg_3 = 0x00020000;
-
-	/* TIMING CFG 1, 533MHz
-	 * PRETOACT: 4 Clocks
-	 * ACTTOPRE: 12 Clocks
-	 * ACTTORW:  4 Clocks
-	 * CASLAT:   4 Clocks
-	 * REFREC:   EXT_REFREC:REFREC 53 Clocks
-	 * WRREC:    4 Clocks
-	 * ACTTOACT: 3 Clocks
-	 * WRTORD:   2 Clocks
-	 */
-	ddr->timing_cfg_1 = 0x4C47D432;
-
-	/* TIMING CFG 2, 533MHz
-	 * ADD_LAT:       3 Clocks
-	 * CPO:           READLAT + 1
-	 * WR_LAT:        3 Clocks
-	 * RD_TO_PRE:     2 Clocks
-	 * WR_DATA_DELAY: 1/2 Clock
-	 * CKE_PLS:       3 Clock
-	 * FOUR_ACT:      14 Clocks
-	 */
-	ddr->timing_cfg_2 = 0x331848CE;
-
-	/* DDR SDRAM Mode, 533MHz
-	 * MRS:          Extended Mode Register
-	 * OUT:          Outputs enabled
-	 * RDQS:         no
-	 * DQS:          enabled
-	 * OCD:          default state
-	 * RTT:          75 Ohms
-	 * Posted CAS:   3 Clocks
-	 * ODS:          reduced strength
-	 * DLL:          enabled
-	 * MR:           Mode Register
-	 * PD:           fast exit
-	 * WR:           4 Clocks
-	 * DLL:          no DLL reset
-	 * TM:           normal
-	 * CAS latency:  4 Clocks
-	 * BT:           sequential
-	 * Burst length: 4
-	 */
-	ddr->sdram_mode = 0x439E0642;
-
-	/* DDR SDRAM Interval, 533MHz
-	 * REFINT:  1040 Clocks
-	 * BSTOPRE: 256
-	 */
-	ddr->sdram_interval = (1040 << 16) | 0x100;
-
-	/*
-	 * Workaround for erratum DDR19 according to MPC8548 Device Errata
-	 * document, Rev. 1: DDR IO receiver must be set to an acceptable
-	 * bias point by modifying a hidden register.
-	 */
-	if (SVR_REV (get_svr ()) < 0x21)
-		gur->ddrioovcr = 0x90000000;	/* enable, VSEL 1.8V */
-
-	/* DDR SDRAM CFG 2
-	 * FRC_SR:      normal mode
-	 * SR_IE:       no self-refresh interrupt
-	 * DLL_RST_DIS: don't care, leave at reset value
-	 * DQS_CFG:     differential DQS signals
-	 * ODT_CFG:     assert ODT to internal IOs only during reads to DRAM
-	 * LVWx_CFG:    don't care, leave at reset value
-	 * NUM_PR:      1 refresh will be issued at a time
-	 * DM_CFG:      don't care, leave at reset value
-	 * D_INIT:      no data initialization
-	 */
-	ddr->sdram_cfg_2 = 0x04401000;
-
-	/* DDR SDRAM MODE 2
-	 * MRS: Extended Mode Register 2
-	 */
-	ddr->sdram_mode_2 = 0x8000C000;
-
-	/* DDR SDRAM CLK CNTL
-	 * CLK_ADJUST: 1/2 Clock 0x02000000
-	 * CLK_ADJUST: 5/8 Clock 0x02800000
-	 */
-	ddr->sdram_clk_cntl = 0x02800000;
-
-	/* wait for clock stabilization */
-	asm ("sync;isync;msync");
-	udelay (1000);
-
-#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
-	/*
-	 * Workaround for erratum DDR20 according to MPC8548 Device Errata
-	 * document, Rev. 1: "CKE signal may not function correctly after
-	 * assertion of HRESET"
-	 */
-
-	/* 1. Configure DDR register as is done in normal DDR configuration.
-	 *    Do not set DDR_SDRAM_CFG[MEM_EN].
-	 *
-	 * 2. Set reserved bit EEBACR[3] at offset 0x1000
-	 */
-	ecm->eebacr |= 0x10000000;
-
-	/*
-	 * 3. Before DDR_SDRAM_CFG[MEM_EN] is set, write DDR_SDRAM_CFG_2[D_INIT]
-	 *
-	 * DDR_SDRAM_CFG_2:
-	 * FRC_SR:      normal mode
-	 * SR_IE:       no self-refresh interrupt
-	 * DLL_RST_DIS: don't care, leave at reset value
-	 * DQS_CFG:     differential DQS signals
-	 * ODT_CFG:     assert ODT to internal IOs only during reads to DRAM
-	 * LVWx_CFG:    don't care, leave at reset value
-	 * NUM_PR:      1 refresh will be issued at a time
-	 * DM_CFG:      don't care, leave at reset value
-	 * D_INIT:      enable data initialization
-	 */
-	ddr->sdram_cfg_2 |= 0x00000010;
-
-	/*
-	 * 4. Before DDR_SDRAM_CFG[MEM_EN] set, write D3[21] to disable data
-	 *    training
-	 */
-	ddr->debug[2] |= 0x00000400;
-
-	/*
-	 * 5. Wait 200 micro-seconds
-	 */
-	udelay (200);
-
-	/*
-	 * 6. Set DDR_SDRAM_CFG[MEM_EN]
-	 *
-	 * BTW, initialize DDR_SDRAM_CFG:
-	 * MEM_EN:       enabled
-	 * SREN:         don't care, leave at reset value
-	 * ECC_EN:       no error report
-	 * RD_EN:        no registered DIMMs
-	 * SDRAM_TYPE:   DDR2
-	 * DYN_PWR:      no power management
-	 * 32_BE:        don't care, leave at reset value
-	 * 8_BE:         4 beat burst
-	 * NCAP:         don't care, leave at reset value
-	 * 2T_EN:        1T Timing
-	 * BA_INTLV_CTL: no interleaving
-	 * x32_EN:       x16 organization
-	 * PCHB8:        MA[10] for auto-precharge
-	 * HSE:          half strength for single and 2-layer stacks
-	 *               (full strength for 3- and 4-layer stacks not
-	 *               yet considered)
-	 * MEM_HALT:     no halt
-	 * BI:           automatic initialization
-	 */
-	ddr->sdram_cfg = 0x83000008;
-
-	/*
-	 * 7. Poll DDR_SDRAM_CFG_2[D_INIT] until it is cleared by hardware
-	 */
-	asm ("sync;isync;msync");
-	while (ddr->sdram_cfg_2 & 0x00000010)
-		asm ("eieio");
-
-	/*
-	 * 8. Clear D3[21] to re-enable data training
-	 */
-	ddr->debug[2] &= ~0x00000400;
-
-	/*
-	 * 9. Set D2(21) to force data training to run
-	 */
-	ddr->debug[1] |= 0x00000400;
-
-	/*
-	 * 10. Poll on D2[21] until it is cleared by hardware
-	 */
-	asm ("sync;isync;msync");
-	while (ddr->debug[1] & 0x00000400)
-		asm ("eieio");
-
-	/*
-	 * 11. Clear reserved bit EEBACR[3] at offset 0x1000
-	 */
-	ecm->eebacr &= ~0x10000000;
-
-#else /* !(CONFIG_TQM8548_AG || CONFIG_TQM8548_BE) */
-
-	/* DDR SDRAM CLK CNTL
-	 * MEM_EN:       enabled
-	 * SREN:         don't care, leave at reset value
-	 * ECC_EN:       no error report
-	 * RD_EN:        no register DIMMs
-	 * SDRAM_TYPE:   DDR2
-	 * DYN_PWR:      no power management
-	 * 32_BE:        don't care, leave at reset value
-	 * 8_BE:         4 beat burst
-	 * NCAP:         don't care, leave at reset value
-	 * 2T_EN:        1T Timing
-	 * BA_INTLV_CTL: no interleaving
-	 * x32_EN:       x16 organization
-	 * PCHB8:        MA[10] for auto-precharge
-	 * HSE:          half strength for single and 2-layer stacks
-	 * (full strength for 3- and 4-layer stacks no yet considered)
-	 * MEM_HALT:     no halt
-	 * BI:           automatic initialization
-	 */
-	ddr->sdram_cfg = 0x83000008;
-
-#endif /* CONFIG_TQM8548_AG || CONFIG_TQM8548_BE */
-
-	asm ("sync; isync; msync");
-	udelay (1000);
-#else /* !CONFIG_TQM8548 */
-	switch (casl) {
-	case 20:
-		cfg_ddr_timing1 = 0x47405331 | (3 << 16);
-		cfg_ddr_mode = 0x40020002 | (2 << 4);
-		break;
-
-	case 25:
-		cfg_ddr_timing1 = 0x47405331 | (4 << 16);
-		cfg_ddr_mode = 0x40020002 | (6 << 4);
-		break;
-
-	case 30:
-	default:
-		cfg_ddr_timing1 = 0x47405331 | (5 << 16);
-		cfg_ddr_mode = 0x40020002 | (3 << 4);
-		break;
-	}
-
-	ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24;
-	ddr->cs0_config = ddr_cs_conf[0].reg;
-	ddr->timing_cfg_1 = cfg_ddr_timing1;
-	ddr->timing_cfg_2 = 0x00000800;		/* P9-45,may need tuning */
-	ddr->sdram_mode = cfg_ddr_mode;
-	ddr->sdram_interval = 0x05160100;	/* autocharge,no open page */
-	ddr->err_disable = 0x0000000D;
-
-	asm ("sync; isync; msync");
-	udelay (1000);
-
-	ddr->sdram_cfg = 0xc2000000;		/* unbuffered,no DYN_PWR */
-	asm ("sync; isync; msync");
-	udelay (1000);
-#endif /* CONFIG_TQM8548 */
-
-	/*
-	 * get_ram_size() depends on having tlbs for the DDR, but they are
-	 * not yet setup because we don't know the size.  Set up a temp
-	 * mapping and delete it when done.
-	 */
-	setup_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
-	for (i = 0; i < N_DDR_CS_CONF; i++) {
-		ddr->cs0_config = ddr_cs_conf[i].reg;
-
-		if (get_ram_size (0, ddr_cs_conf[i].size) ==
-		    ddr_cs_conf[i].size) {
-			/*
-			 * size detected -> set Chip Select Bounds Register
-			 */
-			ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;
-
-			break;
-		}
-	}
-	clear_ddr_tlbs(CONFIG_SYS_DDR_EARLY_SIZE_MB);
-
-#ifdef CONFIG_TQM8548
-	if (i < N_DDR_CS_CONF) {
-		/* Adjust refresh rate for DDR2 */
-
-		ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000;
-
-		ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) |
-		    (ddr_cs_conf[i].refresh & 0x0000F000);
-
-		return ddr_cs_conf[i].size;
-	}
-#endif /* CONFIG_TQM8548 */
-
-	/* return size if detected, else return 0 */
-	return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0;
-}
-
-#if defined(CONFIG_SYS_DRAM_TEST)
-int testdram (void)
-{
-	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
-	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
-	uint *p;
-
-	printf ("SDRAM test phase 1:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0xaaaaaaaa;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0xaaaaaaaa) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf ("SDRAM test phase 2:\n");
-	for (p = pstart; p < pend; p++)
-		*p = 0x55555555;
-
-	for (p = pstart; p < pend; p++) {
-		if (*p != 0x55555555) {
-			printf ("SDRAM test fails at: %08x\n", (uint) p);
-			return 1;
-		}
-	}
-
-	printf ("SDRAM test passed.\n");
-	return 0;
-}
-#endif
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
deleted file mode 100644
index f9f8cc9..0000000
--- a/board/tqc/tqm85xx/tlb.c
+++ /dev/null
@@ -1,214 +0,0 @@ 
-/*
- * Copyright 2008 Freescale Semiconductor, Inc.
- *
- * (C) Copyright 2000
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <asm/mmu.h>
-
-struct fsl_e_tlb_entry tlb_table[] = {
-	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
-		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
-		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
-		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
-		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
-		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
-		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
-		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
-		       0, 0, BOOKE_PAGESZ_4K, 0),
-
-#ifndef CONFIG_TQM_BIGFLASH
-	/*
-	 * TLB 0, 1:	128M	Non-cacheable, guarded
-	 * 0xf8000000	128M	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 1, BOOKE_PAGESZ_64M, 1),
-	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
-		       CONFIG_SYS_FLASH_BASE + 0x4000000,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 0, BOOKE_PAGESZ_64M, 1),
-
-	/*
-	 * TLB 2:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 2, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 3:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 3, BOOKE_PAGESZ_256M, 1),
-
-#ifdef CONFIG_PCIE1
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	PCI express MEM First half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	256M	Non-cacheable, guarded
-	 * 0xd0000000	256M	PCI express MEM Second half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
-		       CONFIG_SYS_PCIE1_MEM_BUS + 0x10000000,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 5, BOOKE_PAGESZ_256M, 1),
-#else /* !CONFIG_PCIE */
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	Rapid IO MEM First half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	256M	Non-cacheable, guarded
-	 * 0xd0000000	256M	Rapid IO MEM Second half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
-		       CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 5, BOOKE_PAGESZ_256M, 1),
-#endif /* CONFIG_PCIE */
-
-	/*
-	 * TLB 6:	 64M	Non-cacheable, guarded
-	 * 0xe0000000	  1M	CCSRBAR
-	 * 0xe2000000	 16M	PCI1 IO
-	 * 0xe3000000	 16M	CAN and NAND Flash
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 6, BOOKE_PAGESZ_64M, 1),
-#ifdef CONFIG_PCIE1
-	/*
-	 * TLB 9:	 16M	Non-cacheable, guarded
-	 * 0xef000000	 16M	PCI express IO
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_BUS,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 9, BOOKE_PAGESZ_16M, 1),
-#endif /* CONFIG_PCIE */
-
-#else /* CONFIG_TQM_BIGFLASH */
-
-	/*
-	 * TLB 0,1,2,3:	  1G	Non-cacheable, guarded
-	 * 0xc0000000	  1G	FLASH
-	 * Out of reset this entry is only 4K.
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 3, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
-		       CONFIG_SYS_FLASH_BASE + 0x10000000,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 2, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
-		       CONFIG_SYS_FLASH_BASE + 0x20000000,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 1, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
-		       CONFIG_SYS_FLASH_BASE + 0x30000000,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 0, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 4:	256M	Non-cacheable, guarded
-	 * 0x80000000	256M	PCI1 MEM First half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 4, BOOKE_PAGESZ_256M, 1),
-
-	/*
-	 * TLB 5:	256M	Non-cacheable, guarded
-	 * 0x90000000	256M	PCI1 MEM Second half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 5, BOOKE_PAGESZ_256M, 1),
-
-#ifdef CONFIG_PCIE1
-	/*
-	 * TLB 6:	256M	Non-cacheable, guarded
-	 * 0xc0000000	256M	PCI express MEM First half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_BUS,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 6, BOOKE_PAGESZ_256M, 1),
-#else /* !CONFIG_PCIE */
-	/*
-	 * TLB 6:	256M	Non-cacheable, guarded
-	 * 0xb0000000	256M	Rapid IO MEM First half
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 6, BOOKE_PAGESZ_256M, 1),
-
-#endif /* CONFIG_PCIE */
-
-	/*
-	 * TLB 7:	 64M	Non-cacheable, guarded
-	 * 0xa0000000	  1M	CCSRBAR
-	 * 0xa2000000	 16M	PCI1 IO
-	 * 0xa3000000	 16M	CAN and NAND Flash
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 7, BOOKE_PAGESZ_64M, 1),
-#ifdef CONFIG_PCIE1
-	/*
-	 * TLB 10:	 16M	Non-cacheable, guarded
-	 * 0xaf000000	 16M	PCI express IO
-	 */
-	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
-		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
-		       0, 10, BOOKE_PAGESZ_16M, 1),
-#endif /* CONFIG_PCIE */
-
-#endif /* CONFIG_TQM_BIGFLASH */
-};
-
-int num_tlb_entries = ARRAY_SIZE (tlb_table);
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
deleted file mode 100644
index 8fb73ab..0000000
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ /dev/null
@@ -1,626 +0,0 @@ 
-/*
- * (C) Copyright 2008 Wolfgang Grandegger <wg@denx.de>
- *
- * (C) Copyright 2006
- * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de.
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003, Motorola Inc.
- * Xianghua Xiao, (X.Xiao@motorola.com)
- *
- * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#include <common.h>
-#include <pci.h>
-#include <asm/processor.h>
-#include <asm/immap_85xx.h>
-#include <asm/fsl_pci.h>
-#include <asm/io.h>
-#include <asm/fsl_serdes.h>
-#include <linux/compiler.h>
-#include <ioports.h>
-#include <flash.h>
-#include <libfdt.h>
-#include <fdt_support.h>
-#include <netdev.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern flash_info_t flash_info[];	/* FLASH chips info */
-
-void local_bus_init (void);
-ulong flash_get_size (ulong base, int banknum);
-
-#ifdef CONFIG_PS2MULT
-void ps2mult_early_init (void);
-#endif
-
-#ifdef CONFIG_CPM2
-/*
- * I/O Port configuration table
- *
- * if conf is 1, then that port pin will be configured at boot time
- * according to the five values podr/pdir/ppar/psor/pdat for that entry
- */
-
-const iop_conf_t iop_conf_tab[4][32] = {
-
-	/* Port A: conf, ppar, psor, pdir, podr, pdat */
-	{
-	 {1, 1, 1, 0, 0, 0},	/* PA31: FCC1 MII COL */
-	 {1, 1, 1, 0, 0, 0},	/* PA30: FCC1 MII CRS */
-	 {1, 1, 1, 1, 0, 0},	/* PA29: FCC1 MII TX_ER */
-	 {1, 1, 1, 1, 0, 0},	/* PA28: FCC1 MII TX_EN */
-	 {1, 1, 1, 0, 0, 0},	/* PA27: FCC1 MII RX_DV */
-	 {1, 1, 1, 0, 0, 0},	/* PA26: FCC1 MII RX_ER */
-	 {0, 1, 0, 1, 0, 0},	/* PA25: FCC1 ATMTXD[0] */
-	 {0, 1, 0, 1, 0, 0},	/* PA24: FCC1 ATMTXD[1] */
-	 {0, 1, 0, 1, 0, 0},	/* PA23: FCC1 ATMTXD[2] */
-	 {0, 1, 0, 1, 0, 0},	/* PA22: FCC1 ATMTXD[3] */
-	 {1, 1, 0, 1, 0, 0},	/* PA21: FCC1 MII TxD[3] */
-	 {1, 1, 0, 1, 0, 0},	/* PA20: FCC1 MII TxD[2] */
-	 {1, 1, 0, 1, 0, 0},	/* PA19: FCC1 MII TxD[1] */
-	 {1, 1, 0, 1, 0, 0},	/* PA18: FCC1 MII TxD[0] */
-	 {1, 1, 0, 0, 0, 0},	/* PA17: FCC1 MII RxD[0] */
-	 {1, 1, 0, 0, 0, 0},	/* PA16: FCC1 MII RxD[1] */
-	 {1, 1, 0, 0, 0, 0},	/* PA15: FCC1 MII RxD[2] */
-	 {1, 1, 0, 0, 0, 0},	/* PA14: FCC1 MII RxD[3] */
-	 {0, 1, 0, 0, 0, 0},	/* PA13: FCC1 ATMRXD[3] */
-	 {0, 1, 0, 0, 0, 0},	/* PA12: FCC1 ATMRXD[2] */
-	 {0, 1, 0, 0, 0, 0},	/* PA11: FCC1 ATMRXD[1] */
-	 {0, 1, 0, 0, 0, 0},	/* PA10: FCC1 ATMRXD[0] */
-	 {0, 1, 1, 1, 0, 0},	/* PA9 : FCC1 L1TXD */
-	 {0, 1, 1, 0, 0, 0},	/* PA8 : FCC1 L1RXD */
-	 {0, 0, 0, 1, 0, 0},	/* PA7 : PA7 */
-	 {0, 1, 1, 1, 0, 0},	/* PA6 : TDM A1 L1RSYNC */
-	 {0, 0, 0, 1, 0, 0},	/* PA5 : PA5 */
-	 {0, 0, 0, 1, 0, 0},	/* PA4 : PA4 */
-	 {0, 0, 0, 1, 0, 0},	/* PA3 : PA3 */
-	 {0, 0, 0, 1, 0, 0},	/* PA2 : PA2 */
-	 {0, 0, 0, 0, 0, 0},	/* PA1 : FREERUN */
-	 {0, 0, 0, 1, 0, 0}	/* PA0 : PA0 */
-	 },
-
-	/* Port B: conf, ppar, psor, pdir, podr, pdat */
-	{
-	 {1, 1, 0, 1, 0, 0},	/* PB31: FCC2 MII TX_ER */
-	 {1, 1, 0, 0, 0, 0},	/* PB30: FCC2 MII RX_DV */
-	 {1, 1, 1, 1, 0, 0},	/* PB29: FCC2 MII TX_EN */
-	 {1, 1, 0, 0, 0, 0},	/* PB28: FCC2 MII RX_ER */
-	 {1, 1, 0, 0, 0, 0},	/* PB27: FCC2 MII COL */
-	 {1, 1, 0, 0, 0, 0},	/* PB26: FCC2 MII CRS */
-	 {1, 1, 0, 1, 0, 0},	/* PB25: FCC2 MII TxD[3] */
-	 {1, 1, 0, 1, 0, 0},	/* PB24: FCC2 MII TxD[2] */
-	 {1, 1, 0, 1, 0, 0},	/* PB23: FCC2 MII TxD[1] */
-	 {1, 1, 0, 1, 0, 0},	/* PB22: FCC2 MII TxD[0] */
-	 {1, 1, 0, 0, 0, 0},	/* PB21: FCC2 MII RxD[0] */
-	 {1, 1, 0, 0, 0, 0},	/* PB20: FCC2 MII RxD[1] */
-	 {1, 1, 0, 0, 0, 0},	/* PB19: FCC2 MII RxD[2] */
-	 {1, 1, 0, 0, 0, 0},	/* PB18: FCC2 MII RxD[3] */
-	 {1, 1, 0, 0, 0, 0},	/* PB17: FCC3:RX_DIV */
-	 {1, 1, 0, 0, 0, 0},	/* PB16: FCC3:RX_ERR */
-	 {1, 1, 0, 1, 0, 0},	/* PB15: FCC3:TX_ERR */
-	 {1, 1, 0, 1, 0, 0},	/* PB14: FCC3:TX_EN */
-	 {1, 1, 0, 0, 0, 0},	/* PB13: FCC3:COL */
-	 {1, 1, 0, 0, 0, 0},	/* PB12: FCC3:CRS */
-	 {1, 1, 0, 0, 0, 0},	/* PB11: FCC3:RXD */
-	 {1, 1, 0, 0, 0, 0},	/* PB10: FCC3:RXD */
-	 {1, 1, 0, 0, 0, 0},	/* PB9 : FCC3:RXD */
-	 {1, 1, 0, 0, 0, 0},	/* PB8 : FCC3:RXD */
-	 {1, 1, 0, 1, 0, 0},	/* PB7 : FCC3:TXD */
-	 {1, 1, 0, 1, 0, 0},	/* PB6 : FCC3:TXD */
-	 {1, 1, 0, 1, 0, 0},	/* PB5 : FCC3:TXD */
-	 {1, 1, 0, 1, 0, 0},	/* PB4 : FCC3:TXD */
-	 {0, 0, 0, 0, 0, 0},	/* PB3 : pin doesn't exist */
-	 {0, 0, 0, 0, 0, 0},	/* PB2 : pin doesn't exist */
-	 {0, 0, 0, 0, 0, 0},	/* PB1 : pin doesn't exist */
-	 {0, 0, 0, 0, 0, 0}	/* PB0 : pin doesn't exist */
-	 },
-
-	/* Port C: conf, ppar, psor, pdir, podr, pdat */
-	{
-	 {0, 0, 0, 1, 0, 0},	/* PC31: PC31 */
-	 {0, 0, 0, 1, 0, 0},	/* PC30: PC30 */
-	 {0, 1, 1, 0, 0, 0},	/* PC29: SCC1 EN *CLSN */
-	 {0, 0, 0, 1, 0, 0},	/* PC28: PC28 */
-	 {0, 0, 0, 1, 0, 0},	/* PC27: UART Clock in */
-	 {0, 0, 0, 1, 0, 0},	/* PC26: PC26 */
-	 {0, 0, 0, 1, 0, 0},	/* PC25: PC25 */
-	 {0, 0, 0, 1, 0, 0},	/* PC24: PC24 */
-	 {0, 1, 0, 1, 0, 0},	/* PC23: ATMTFCLK */
-	 {0, 1, 0, 0, 0, 0},	/* PC22: ATMRFCLK */
-	 {1, 1, 0, 0, 0, 0},	/* PC21: SCC1 EN RXCLK */
-	 {1, 1, 0, 0, 0, 0},	/* PC20: SCC1 EN TXCLK */
-	 {1, 1, 0, 0, 0, 0},	/* PC19: FCC2 MII RX_CLK CLK13 */
-	 {1, 1, 0, 0, 0, 0},	/* PC18: FCC Tx Clock (CLK14) */
-	 {1, 1, 0, 0, 0, 0},	/* PC17: PC17 */
-	 {1, 1, 0, 0, 0, 0},	/* PC16: FCC Tx Clock (CLK16) */
-	 {0, 1, 0, 0, 0, 0},	/* PC15: PC15 */
-	 {0, 1, 0, 0, 0, 0},	/* PC14: SCC1 EN *CD */
-	 {0, 1, 0, 0, 0, 0},	/* PC13: PC13 */
-	 {0, 1, 0, 1, 0, 0},	/* PC12: PC12 */
-	 {0, 0, 0, 1, 0, 0},	/* PC11: LXT971 transmit control */
-	 {0, 0, 0, 1, 0, 0},	/* PC10: FETHMDC */
-	 {0, 0, 0, 0, 0, 0},	/* PC9 : FETHMDIO */
-	 {0, 0, 0, 1, 0, 0},	/* PC8 : PC8 */
-	 {0, 0, 0, 1, 0, 0},	/* PC7 : PC7 */
-	 {0, 0, 0, 1, 0, 0},	/* PC6 : PC6 */
-	 {0, 0, 0, 1, 0, 0},	/* PC5 : PC5 */
-	 {0, 0, 0, 1, 0, 0},	/* PC4 : PC4 */
-	 {0, 0, 0, 1, 0, 0},	/* PC3 : PC3 */
-	 {0, 0, 0, 1, 0, 1},	/* PC2 : ENET FDE */
-	 {0, 0, 0, 1, 0, 0},	/* PC1 : ENET DSQE */
-	 {0, 0, 0, 1, 0, 0},	/* PC0 : ENET LBK */
-	 },
-
-	/* Port D: conf, ppar, psor, pdir, podr, pdat */
-	{
-#ifdef CONFIG_TQM8560
-	 {1, 1, 0, 0, 0, 0},	/* PD31: SCC1 EN RxD */
-	 {1, 1, 1, 1, 0, 0},	/* PD30: SCC1 EN TxD */
-	 {1, 1, 0, 1, 0, 0},	/* PD29: SCC1 EN TENA */
-#else /* !CONFIG_TQM8560 */
-	 {0, 0, 0, 0, 0, 0},	/* PD31: PD31 */
-	 {0, 0, 0, 0, 0, 0},	/* PD30: PD30 */
-	 {0, 0, 0, 0, 0, 0},	/* PD29: PD29 */
-#endif /* CONFIG_TQM8560 */
-	 {1, 1, 0, 0, 0, 0},	/* PD28: PD28 */
-	 {1, 1, 0, 1, 0, 0},	/* PD27: PD27 */
-	 {1, 1, 0, 1, 0, 0},	/* PD26: PD26 */
-	 {0, 0, 0, 1, 0, 0},	/* PD25: PD25 */
-	 {0, 0, 0, 1, 0, 0},	/* PD24: PD24 */
-	 {0, 0, 0, 1, 0, 0},	/* PD23: PD23 */
-	 {0, 0, 0, 1, 0, 0},	/* PD22: PD22 */
-	 {0, 0, 0, 1, 0, 0},	/* PD21: PD21 */
-	 {0, 0, 0, 1, 0, 0},	/* PD20: PD20 */
-	 {0, 0, 0, 1, 0, 0},	/* PD19: PD19 */
-	 {0, 0, 0, 1, 0, 0},	/* PD18: PD18 */
-	 {0, 1, 0, 0, 0, 0},	/* PD17: FCC1 ATMRXPRTY */
-	 {0, 1, 0, 1, 0, 0},	/* PD16: FCC1 ATMTXPRTY */
-	 {0, 1, 1, 0, 1, 0},	/* PD15: I2C SDA */
-	 {0, 0, 0, 1, 0, 0},	/* PD14: LED */
-	 {0, 0, 0, 0, 0, 0},	/* PD13: PD13 */
-	 {0, 0, 0, 0, 0, 0},	/* PD12: PD12 */
-	 {0, 0, 0, 0, 0, 0},	/* PD11: PD11 */
-	 {0, 0, 0, 0, 0, 0},	/* PD10: PD10 */
-	 {0, 1, 0, 1, 0, 0},	/* PD9 : SMC1 TXD */
-	 {0, 1, 0, 0, 0, 0},	/* PD8 : SMC1 RXD */
-	 {0, 0, 0, 1, 0, 1},	/* PD7 : PD7 */
-	 {0, 0, 0, 1, 0, 1},	/* PD6 : PD6 */
-	 {0, 0, 0, 1, 0, 1},	/* PD5 : PD5 */
-	 {0, 0, 0, 1, 0, 1},	/* PD4 : PD4 */
-	 {0, 0, 0, 0, 0, 0},	/* PD3 : pin doesn't exist */
-	 {0, 0, 0, 0, 0, 0},	/* PD2 : pin doesn't exist */
-	 {0, 0, 0, 0, 0, 0},	/* PD1 : pin doesn't exist */
-	 {0, 0, 0, 0, 0, 0}	/* PD0 : pin doesn't exist */
-	 }
-};
-#endif /*  CONFIG_CPM2 */
-
-#define CASL_STRING1	"casl=xx"
-#define CASL_STRING2	"casl="
-
-static const int casl_table[] = { 20, 25, 30 };
-#define	N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))
-
-int cas_latency (void)
-{
-	char buf[128];
-	int casl;
-	int val;
-	int i;
-
-	casl = CONFIG_DDR_DEFAULT_CL;
-
-	i = getenv_f("serial#", buf, sizeof(buf));
-
-	if (i >0) {
-		if (strncmp(buf + strlen (buf) - strlen (CASL_STRING1),
-			    CASL_STRING2, strlen (CASL_STRING2)) == 0) {
-			val = simple_strtoul (buf + strlen (buf) - 2, NULL, 10);
-
-			for (i = 0; i < N_CASL; ++i) {
-				if (val == casl_table[i]) {
-					return val;
-				}
-			}
-		}
-	}
-
-	return casl;
-}
-
-int checkboard (void)
-{
-	char buf[64];
-	int i = getenv_f("serial#", buf, sizeof(buf));
-
-	printf ("Board: %s", CONFIG_BOARDNAME);
-	if (i > 0) {
-		puts(", serial# ");
-		puts(buf);
-	}
-	putc ('\n');
-
-	/*
-	 * Initialize local bus.
-	 */
-	local_bus_init ();
-
-	return 0;
-}
-
-int misc_init_r (void)
-{
-	/*
-	 * Adjust flash start and offset to detected values
-	 */
-	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
-	gd->bd->bi_flashoffset = 0;
-
-	/*
-	 * Recalculate CS configuration if second FLASH bank is available
-	 */
-	if (flash_info[0].size > 0) {
-		set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
-			   (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
-		set_lbc_br(1, gd->bd->bi_flashstart |
-			   (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
-		/*
-		 * Re-check to get correct base address for bank 1
-		 */
-		flash_get_size (gd->bd->bi_flashstart, 0);
-	} else {
-		set_lbc_or(1, 0);
-		set_lbc_br(1, 0);
-	}
-
-	/*
-	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
-	 */
-	set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
-		   (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
-	set_lbc_br(0, (gd->bd->bi_flashstart + flash_info[0].size) |
-		   (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
-
-	/*
-	 * Re-check to get correct base address for bank 0
-	 */
-	flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);
-
-	/*
-	 * Re-do flash protection upon new addresses
-	 */
-	flash_protect (FLAG_PROTECT_CLEAR,
-		       gd->bd->bi_flashstart, 0xffffffff,
-		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-	/* Monitor protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_SYS_MONITOR_BASE, 0xffffffff,
-		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-	/* Environment protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR,
-		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-
-#ifdef CONFIG_ENV_ADDR_REDUND
-	/* Redundant environment protection ON by default */
-	flash_protect (FLAG_PROTECT_SET,
-		       CONFIG_ENV_ADDR_REDUND,
-		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
-#endif
-
-	return 0;
-}
-
-#ifdef CONFIG_CAN_DRIVER
-/*
- * Initialize UPMC RAM
- */
-static void upmc_write (u_char addr, uint val)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-
-	out_be32 (&lbc->mdr, val);
-
-	clrsetbits_be32(&lbc->mcmr, MxMR_MAD_MSK,
-			MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
-
-	/* dummy access to perform write */
-	out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
-
-	/* normal operation */
-	clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
-}
-#endif /* CONFIG_CAN_DRIVER */
-
-uint get_lbc_clock (void)
-{
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	sys_info_t sys_info;
-	ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
-
-	get_sys_info (&sys_info);
-
-	if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) {
-#ifdef CONFIG_MPC8548
-		/*
-		 * Yes, the entire PQ38 family use the same
-		 * bit-representation for twice the clock divider value.
-		 */
-		clkdiv *= 2;
-#endif
-		return sys_info.freqSystemBus / clkdiv;
-	}
-
-	puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
-
-	return 0;
-}
-
-/*
- * Initialize Local Bus
- */
-void local_bus_init (void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
-	uint lbc_mhz = get_lbc_clock ()  / 1000000;
-
-#ifdef CONFIG_MPC8548
-	uint svr = get_svr ();
-	uint lcrr;
-
-	/*
-	 * MPC revision < 2.0
-	 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1:
-	 * Modify engineering use only register at address 0xE_0F20.
-	 * "1. Read register at offset 0xE_0F20
-	 * 2. And value with 0x0000_FFFF
-	 * 3. OR result with 0x0000_0004
-	 * 4. Write result back to offset 0xE_0F20."
-	 *
-	 * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2:
-	 * Modify engineering use only register at address 0xE_0F20.
-	 * "1. Read register at offset 0xE_0F20
-	 * 2. And value with 0xFFFF_FFDF
-	 * 3. Write result back to offset 0xE_0F20."
-	 *
-	 * Since it is the same register, we do the modification in one step.
-	 */
-	if (SVR_MAJ (svr) < 2) {
-		uint dummy = gur->lbiuiplldcr1;
-		dummy &= 0x0000FFDF;
-		dummy |= 0x00000004;
-		gur->lbiuiplldcr1 = dummy;
-	}
-
-	lcrr = CONFIG_SYS_LBC_LCRR;
-
-	/*
-	 * Local Bus Clock > 83.3 MHz. According to timing
-	 * specifications set LCRR[EADC] to 2 delay cycles.
-	 */
-	if (lbc_mhz > 83) {
-		lcrr &= ~LCRR_EADC;
-		lcrr |= LCRR_EADC_2;
-	}
-
-	/*
-	 * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30
-	 * disable PLL bypass for Local Bus Clock > 83 MHz.
-	 */
-	if (lbc_mhz >= 66)
-		lcrr &= (~LCRR_DBYP);	/* DLL Enabled */
-
-	else
-		lcrr |= LCRR_DBYP;	/* DLL Bypass */
-
-	lbc->lcrr = lcrr;
-	asm ("sync;isync;msync");
-
-	/*
-	 * According to MPC8548ERMAD Rev.1.3 read back LCRR
-	 * and terminate with isync
-	 */
-	lcrr = lbc->lcrr;
-	asm ("isync;");
-
-	/* let DLL stabilize */
-	udelay (500);
-
-#else /* !CONFIG_MPC8548 */
-
-	/*
-	 * Errata LBC11.
-	 * Fix Local Bus clock glitch when DLL is enabled.
-	 *
-	 * If localbus freq is < 66MHz, DLL bypass mode must be used.
-	 * If localbus freq is > 133MHz, DLL can be safely enabled.
-	 * Between 66 and 133, the DLL is enabled with an override workaround.
-	 */
-
-	if (lbc_mhz < 66) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
-		lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
-			     LTEDR_RAWA | LTEDR_CSD;	/* Disable all error checking */
-
-	} else if (lbc_mhz >= 133) {
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
-
-	} else {
-		/*
-		 * On REV1 boards, need to change CLKDIV before enable DLL.
-		 * Default CLKDIV is 8, change it to 4 temporarily.
-		 */
-		uint pvr = get_pvr ();
-		uint temp_lbcdll = 0;
-
-		if (pvr == PVR_85xx_REV1) {
-			/* FIXME: Justify the high bit here. */
-			lbc->lcrr = 0x10000004;
-		}
-
-		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
-		udelay (200);
-
-		/*
-		 * Sample LBC DLL ctrl reg, upshift it to set the
-		 * override bits.
-		 */
-		temp_lbcdll = gur->lbcdllcr;
-		gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
-		asm ("sync;isync;msync");
-	}
-#endif /* !CONFIG_MPC8548 */
-
-#ifdef	CONFIG_CAN_DRIVER
-	/*
-	 * According to timing specifications EAD must be
-	 * set if Local Bus Clock is > 83 MHz.
-	 */
-	if (lbc_mhz > 83)
-		set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
-	else
-		set_lbc_or(2, CONFIG_SYS_OR2_CAN);
-	set_lbc_br(2, CONFIG_SYS_BR2_CAN);
-
-	/* LGPL4 is UPWAIT */
-	out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
-
-	/* Initialize UPMC for CAN: single read */
-	upmc_write (0x00, 0xFFFFED00);
-	upmc_write (0x01, 0xCCFFCC00);
-	upmc_write (0x02, 0x00FFCF00);
-	upmc_write (0x03, 0x00FFCF00);
-	upmc_write (0x04, 0x00FFDC00);
-	upmc_write (0x05, 0x00FFCF00);
-	upmc_write (0x06, 0x00FFED00);
-	upmc_write (0x07, 0x3FFFCC07);
-
-	/* Initialize UPMC for CAN: single write */
-	upmc_write (0x18, 0xFFFFED00);
-	upmc_write (0x19, 0xCCFFEC00);
-	upmc_write (0x1A, 0x00FFED80);
-	upmc_write (0x1B, 0x00FFED80);
-	upmc_write (0x1C, 0x00FFFC00);
-	upmc_write (0x1D, 0x0FFFEC00);
-	upmc_write (0x1E, 0x0FFFEF00);
-	upmc_write (0x1F, 0x3FFFEC05);
-#endif /* CONFIG_CAN_DRIVER */
-}
-
-/*
- * Initialize PCI Devices, report devices found.
- */
-
-#ifdef CONFIG_PCI1
-static struct pci_controller pci1_hose;
-#endif /* CONFIG_PCI1 */
-
-void pci_init_board (void)
-{
-	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
-	int first_free_busno = 0;
-#ifdef CONFIG_PCI1
-	struct fsl_pci_info pci_info;
-	int pcie_ep;
-
-	u32 devdisr = in_be32(&gur->devdisr);
-
-	uint pci_32 = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_PCI32;
-	uint pci_arb = in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1_ARB;
-	uint pci_speed = CONFIG_SYS_CLK_FREQ;	/* PCI PSPEED in [4:5] */
-	uint pci_clk_sel = in_be32(&gur->porpllsr) & MPC85xx_PORDEVSR_PCI1_SPD;
-
-	if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
-		SET_STD_PCI_INFO(pci_info, 1);
-		set_next_law(pci_info.mem_phys,
-			law_size_bits(pci_info.mem_size), pci_info.law);
-		set_next_law(pci_info.io_phys,
-			law_size_bits(pci_info.io_size), pci_info.law);
-
-		pcie_ep = fsl_setup_hose(&pci1_hose, pci_info.regs);
-		printf("PCI1:  %d bit, %s MHz, %s, %s, %s\n",
-			(pci_32) ? 32 : 64,
-			(pci_speed == 33333333) ? "33" :
-			(pci_speed == 66666666) ? "66" : "unknown",
-			pci_clk_sel ? "sync" : "async",
-			pcie_ep ? "agent" : "host",
-			pci_arb ? "arbiter" : "external-arbiter");
-		first_free_busno = fsl_pci_init_port(&pci_info,
-					&pci1_hose, first_free_busno);
-#ifdef CONFIG_PCIX_CHECK
-		if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_PCI1)) {
-			ushort reg16 =
-				PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ |
-				PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
-			uint dev = PCI_BDF(0, 0, 0);
-
-			/* PCI-X init */
-			if (CONFIG_SYS_CLK_FREQ < 66000000)
-				puts ("PCI-X will only work at 66 MHz\n");
-
-			pci_write_config_word(dev, PCIX_COMMAND, reg16);
-		}
-#endif
-	} else {
-		printf("PCI1: disabled\n");
-	}
-#else
-	setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1);
-#endif
-
-	fsl_pcie_init_board(first_free_busno);
-}
-
-#ifdef CONFIG_OF_BOARD_SETUP
-void ft_board_setup (void *blob, bd_t *bd)
-{
-	ft_cpu_setup (blob, bd);
-
-	FT_FSL_PCI_SETUP;
-}
-#endif /* CONFIG_OF_BOARD_SETUP */
-
-#ifdef CONFIG_BOARD_EARLY_INIT_R
-int board_early_init_r (void)
-{
-#ifdef CONFIG_PS2MULT
-	ps2mult_early_init ();
-#endif /* CONFIG_PS2MULT */
-	return (0);
-}
-#endif /* CONFIG_BOARD_EARLY_INIT_R */
-
-int board_eth_init(bd_t *bis)
-{
-	cpu_eth_init(bis);	/* Intialize TSECs first */
-	return pci_eth_init(bis);
-}
diff --git a/boards.cfg b/boards.cfg
index f789539..26062c2 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -831,13 +831,6 @@  BSC9131RDB_SPIFLASH          powerpc     mpc85xx     bsc9131rdb          freesca
 stxgp3                       powerpc     mpc85xx     stxgp3              stx
 stxssa                       powerpc     mpc85xx     stxssa              stx            -           stxssa
 stxssa_4M                    powerpc     mpc85xx     stxssa              stx            -           stxssa:STXSSA_4M
-TQM8540                      powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8540,TQM8540=y,HOSTNAME=tqm8540,BOARDNAME="TQM8540"
-TQM8541                      powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8541,TQM8541=y,HOSTNAME=tqm8541,BOARDNAME="TQM8541"
-TQM8548                      powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8548,TQM8548=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548"
-TQM8548_AG                   powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8548,TQM8548_AG=y,HOSTNAME=tqm8485,BOARDNAME="TQM8548_AG"
-TQM8548_BE                   powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8548,TQM8548_BE=y,HOSTNAME=tqm8548,BOARDNAME="TQM8548_BE"
-TQM8555                      powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8555,TQM8555=y,HOSTNAME=tqm8555,BOARDNAME="TQM8555"
-TQM8560                      powerpc     mpc85xx     tqm85xx             tqc            -           TQM85xx:MPC8560,TQM8560=y,HOSTNAME=tqm8560,BOARDNAME="TQM8560"
 xpedite520x                  powerpc     mpc85xx     -                   xes
 xpedite537x                  powerpc     mpc85xx     -                   xes
 xpedite550x                  powerpc     mpc85xx     -                   xes
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 5929a8e..d0f4716 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -11,8 +11,9 @@  easily if here is something they might want to dig for...
 
 Board	Arch	CPU	removed	    Commit	last known maintainer/contact
 =============================================================================
-apollon arm     omap24xx -        2012-09-06    Kyungmin Park <kyungmin.park@samsung.com>
-tb0229	mips	mips32	-	  2011-12-12
+TQM85xx	powerpc	MPC85xx	-	  -		Stefan Roese <sr@denx.de>
+apollon arm     omap24xx 535c74f  2012-09-18    Kyungmin Park <kyungmin.park@samsung.com>
+tb0229	mips	mips32	3f3110d	  2011-12-12
 rmu	powerpc	MPC850	fb82fd7   2011-12-07	Wolfgang Denk <wd@denx.de>
 OXC	powerpc	MPC8240	309a292   2011-12-07
 BAB7xx	powerpc	MPC740/MPC750 c53043b 2011-12-07 Frank Gottschling <fgottschling@eltec.de>
diff --git a/drivers/mtd/nand/fsl_upm.c b/drivers/mtd/nand/fsl_upm.c
index 31c174b..11eb167 100644
--- a/drivers/mtd/nand/fsl_upm.c
+++ b/drivers/mtd/nand/fsl_upm.c
@@ -57,7 +57,7 @@  static void fun_wait(struct fsl_upm_nand *fun)
 			debug("unexpected busy state\n");
 	} else {
 		/*
-		 * If the R/B pin is not connected, like on the TQM8548,
+		 * If the R/B pin is not connected,
 		 * a short delay is necessary.
 		 */
 		udelay(1);
@@ -115,10 +115,10 @@  static void fun_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 	fsl_upm_run_pattern(&fun->upm, fun->width, io_addr, mar);
 
 	/*
-	 * Some boards/chips needs this. At least the MPC8360E-RDK and
-	 * TQM8548 need it. Probably weird chip, because I don't see
-	 * any need for this on MPC8555E + Samsung K9F1G08U0A. Usually
-	 * here are 0-2 unexpected busy states per block read.
+         * Some boards/chips needs this.  At least the MPC8360E-RDK
+         * needs it.  Probably weird chip, because I don't see any
+         * need for this on MPC8555E + Samsung K9F1G08U0A.  Usually
+         * here are 0-2 unexpected busy states per block read.
 	 */
 	if (fun->wait_flags & FSL_UPM_WAIT_RUN_PATTERN)
 		fun_wait(fun);
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
deleted file mode 100644
index 95455c4..0000000
--- a/include/configs/TQM85xx.h
+++ /dev/null
@@ -1,697 +0,0 @@ 
-/*
- * (C) Copyright 2007
- * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de.
- *
- * (C) Copyright 2005
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * Wolfgang Denk <wd@denx.de>
- * Copyright 2004 Freescale Semiconductor.
- * (C) Copyright 2002,2003 Motorola,Inc.
- * Xianghua Xiao <X.Xiao@motorola.com>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-/*
- * TQM85xx (8560/40/55/41/48) board configuration file
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/* High Level Configuration Options */
-#define CONFIG_BOOKE		1	/* BOOKE			*/
-#define CONFIG_E500		1	/* BOOKE e500 family		*/
-#define CONFIG_MPC85xx		1	/* MPC8540/60/55/41		*/
-
-#if defined(CONFIG_TQM8548_BE)
-#define CONFIG_SYS_TEXT_BASE	0xfff80000
-#else
-#define CONFIG_SYS_TEXT_BASE	0xfffc0000
-#endif
-
-#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
-#define CONFIG_TQM8548
-#endif
-
-#define CONFIG_PCI
-#ifndef CONFIG_TQM8548_AG
-#define CONFIG_PCI1			/* PCI/PCI-X controller		*/
-#endif
-#ifdef CONFIG_TQM8548
-#define CONFIG_PCIE1			/* PCI Express interface	*/
-#endif
-
-#define CONFIG_FSL_PCI_INIT	1	/* Use common FSL init code	*/
-#define CONFIG_PCIX_CHECK		/* PCIX olny works at 66 MHz	*/
-#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata	*/
-
-#define CONFIG_TSEC_ENET		/* tsec ethernet support	*/
-
-#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
-
- /*
- * Configuration for big NOR Flashes
- *
- * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash.
- * Please be aware, that this changes the whole memory map (new CCSRBAR
- * address, etc). You have to use an adapted Linux kernel or FDT blob
- * if this option is set.
- */
-#undef CONFIG_TQM_BIGFLASH
-
-/*
- * NAND flash support (disabled by default)
- *
- * Warning: NAND support will likely increase the U-Boot image size
- * to more than 256 KB. Please adjust CONFIG_SYS_TEXT_BASE if necessary.
- */
-#ifdef CONFIG_TQM8548_BE
-#define CONFIG_NAND
-#endif
-
-/*
- * MPC8540 and MPC8548 don't have CPM module
- */
-#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548)
-#define CONFIG_CPM2		1	/* has CPM2			*/
-#endif
-
-#define CONFIG_FSL_LAW		1	/* Use common FSL init code	*/
-
-#if defined(CONFIG_TQM8548_AG) || defined(CONFIG_TQM8548_BE)
-#define	CONFIG_CAN_DRIVER		/* CAN Driver support		*/
-#endif
-
-/*
- * sysclk for MPC85xx
- *
- * Two valid values are:
- *    33333333
- *    66666666
- *
- * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
- * is likely the desired value here, so that is now the default.
- * The board, however, can run at 66MHz.  In any event, this value
- * must match the settings of some switches.  Details can be found
- * in the README.mpc85xxads.
- */
-
-#ifndef CONFIG_SYS_CLK_FREQ
-#define CONFIG_SYS_CLK_FREQ	33333333
-#endif
-
-/*
- * These can be toggled for performance analysis, otherwise use default.
- */
-#define CONFIG_L2_CACHE			/* toggle L2 cache		*/
-#define CONFIG_BTB			/* toggle branch predition	*/
-
-#define CONFIG_SYS_INIT_DBCR DBCR_IDM		/* Enable Debug Exceptions	*/
-
-#undef	CONFIG_SYS_DRAM_TEST			/* memory test, takes time	*/
-#define CONFIG_SYS_MEMTEST_START	0x00000000
-#define CONFIG_SYS_MEMTEST_END		0x10000000
-
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_CCSRBAR	 	0xA0000000
-#else
-#define CONFIG_SYS_CCSRBAR		0xE0000000
-#endif
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
-
-/*
- * DDR Setup
- */
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
-
-#if defined(CONFIG_TQM_BIGFLASH) || \
-	(!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE))
-#define CONFIG_SYS_PPC_DDR_WIMGE (MAS2_I | MAS2_G)
-#define CONFIG_SYS_DDR_EARLY_SIZE_MB	(512)
-#else
-#define CONFIG_SYS_PPC_DDR_WIMGE (0)
-#define CONFIG_SYS_DDR_EARLY_SIZE_MB	(2 * 1024)
-#endif
-
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
-#ifdef CONFIG_TQM8548_AG
-#define CONFIG_VERY_BIG_RAM
-#endif
-
-#define CONFIG_NUM_DDR_CONTROLLERS	1
-#define CONFIG_DIMM_SLOTS_PER_CTLR	1
-#define CONFIG_CHIP_SELECTS_PER_CTRL	2
-
-#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
-/* TQM8540 & 8560 need DLL-override */
-#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN	/* possible DLL fix needed */
-#define CONFIG_DDR_DEFAULT_CL	25		/* CAS latency 2,5	*/
-#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
-
-#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \
-    defined(CONFIG_TQM8548)
-#define CONFIG_DDR_DEFAULT_CL	30		/* CAS latency 3	*/
-#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */
-
-/*
- * Flash on the Local Bus
- */
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_FLASH0		0xE0000000
-#define CONFIG_SYS_FLASH1		0xC0000000
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_FLASH0		0xFC000000
-#define CONFIG_SYS_FLASH1		0xF8000000
-#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
-
-#define CONFIG_SYS_LBC_FLASH_BASE	CONFIG_SYS_FLASH1	/* Localbus flash start	*/
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_LBC_FLASH_BASE  /* start of FLASH	*/
-
-/* Default ORx timings are for <= 41.7 MHz Local Bus Clock.
- *
- * Note: According to timing specifications external addr latch delay
- * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz.
- *
- * For other Local Bus Clocks see following table:
- *
- * Clock/MHz   CONFIG_SYS_ORx_PRELIM
- * 166         0x.....CA5
- * 133         0x.....C85
- * 100         0x.....C65
- *  83         0x.....FA2
- *  66         0x.....C82
- *  50         0x.....C60
- *  42         0x.....040
- *  33         0x.....030
- *  25         0x.....020
- *
- */
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_BR0_PRELIM		0xE0001801	/* port size 32bit	*/
-#define CONFIG_SYS_OR0_PRELIM		0xE0000040	/* 512MB Flash		*/
-#define CONFIG_SYS_BR1_PRELIM		0xC0001801	/* port size 32bit	*/
-#define CONFIG_SYS_OR1_PRELIM		0xE0000040	/* 512MB Flash		*/
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_BR0_PRELIM		0xfc001801	/* port size 32bit	*/
-#define CONFIG_SYS_OR0_PRELIM		0xfc000040	/* 64MB Flash		*/
-#define CONFIG_SYS_BR1_PRELIM		0xf8001801	/* port size 32bit	*/
-#define CONFIG_SYS_OR1_PRELIM		0xfc000040	/* 64MB Flash		*/
-#endif /* CONFIG_TQM_BIGFLASH */
-
-#define CONFIG_SYS_FLASH_CFI			/* flash is CFI compat.		*/
-#define CONFIG_FLASH_CFI_DRIVER		/* Use common CFI driver	*/
-#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector	*/
-#define CONFIG_SYS_FLASH_QUIET_TEST	1	/* don't warn upon unknown flash*/
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1 /* speed up output to Flash	*/
-
-#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* number of banks		*/
-#define CONFIG_SYS_MAX_FLASH_SECT	512	/* sectors per device		*/
-#undef	CONFIG_SYS_FLASH_CHECKSUM
-#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms)	*/
-#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms)	*/
-
-#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor	*/
-
-/*
- * Note: when changing the Local Bus clock divider you have to
- * change the timing values in CONFIG_SYS_ORx_PRELIM.
- *
- * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8.
- * LCRR[16:17] EADC  : External address delay cycles. It should be set to 2
- *                     for Local Bus Clock > 83.3 MHz.
- */
-#define CONFIG_SYS_LBC_LCRR		0x00030008	/* LB clock ratio reg	*/
-#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg	*/
-#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR		0x20000000	/* LB refresh timer presc.*/
-
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	(CONFIG_SYS_CCSRBAR \
-				 + 0x04010000)	/* Initial RAM address	*/
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size used area in RAM	*/
-
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
-
-#define CONFIG_SYS_MONITOR_LEN		(~CONFIG_SYS_TEXT_BASE + 1)/* Reserved for Monitor	*/
-#define CONFIG_SYS_MALLOC_LEN		(384 * 1024)	/* Reserved for malloc	*/
-
-/* Serial Port */
-#if defined(CONFIG_TQM8560)
-
-#define CONFIG_CONS_ON_SCC	/* define if console on SCC		*/
-#undef	CONFIG_CONS_NONE	/* define if console on something else	*/
-#define CONFIG_CONS_INDEX	1 /* which serial channel for console	*/
-
-#else /* !CONFIG_TQM8560 */
-
-#define CONFIG_CONS_INDEX     1
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
-
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
-
-/* PS/2 Keyboard */
-#define CONFIG_PS2KBD			/* AT-PS/2 Keyboard		*/
-#define CONFIG_PS2MULT			/* .. on PS/2 Multiplexer	*/
-#define CONFIG_PS2SERIAL	2	/* .. on DUART2			*/
-#define CONFIG_PS2MULT_DELAY	(CONFIG_SYS_HZ/2)	/* Initial delay	*/
-#define CONFIG_BOARD_EARLY_INIT_R	1
-
-#endif /* CONFIG_TQM8560 */
-
-#define CONFIG_BAUDRATE		115200
-
-#define CONFIG_SYS_BAUDRATE_TABLE	\
-	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
-
-#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
-#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support */
-#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/
-
-/* pass open firmware flat tree */
-#define CONFIG_OF_LIBFDT		1
-#define CONFIG_OF_BOARD_SETUP		1
-#define CONFIG_OF_STDOUT_VIA_ALIAS	1
-
-/* CAN */
-#define CONFIG_SYS_CAN_BASE		(CONFIG_SYS_CCSRBAR \
-				 + 0x03000000)	/* CAN base address     */
-#ifdef CONFIG_CAN_DRIVER
-#define CONFIG_SYS_CAN_OR_AM		0xFFFF8000	/* 32 KiB address mask  */
-#define CONFIG_SYS_OR2_CAN		(CONFIG_SYS_CAN_OR_AM | OR_UPM_BI)
-#define CONFIG_SYS_BR2_CAN		((CONFIG_SYS_CAN_BASE & BR_BA) | \
-				 BR_PS_8 | BR_MS_UPMC | BR_V)
-#endif /* CONFIG_CAN_DRIVER */
-
-/*
- * I2C
- */
-#define CONFIG_FSL_I2C			/* Use FSL common I2C driver	*/
-#define CONFIG_HARD_I2C			/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CONFIG_SYS_I2C_SLAVE		0x7F
-#define CONFIG_SYS_I2C_NOPROBES	{0x48}	/* Don't probe these addrs	*/
-#define CONFIG_SYS_I2C_OFFSET		0x3000
-
-/* I2C RTC */
-#define CONFIG_RTC_DS1337		/* Use ds1337 rtc via i2c	*/
-#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/
-
-/* I2C EEPROM */
-/*
- * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
- */
-#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50	/* 1010000x		*/
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20
-#define CONFIG_SYS_I2C_MULTI_EEPROMS		1	/* more than one eeprom	*/
-
-/* I2C SYSMON (LM75) */
-#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
-#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
-#define CONFIG_SYS_DTT_MAX_TEMP	70
-#define CONFIG_SYS_DTT_LOW_TEMP	-30
-#define CONFIG_SYS_DTT_HYSTERESIS	3
-
-#ifndef CONFIG_PCIE1
-/* RapidIO MMU */
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_RIO_MEM_BASE	0xb0000000	/* base address		*/
-#define CONFIG_SYS_RIO_MEM_SIZE	0x10000000	/* 256M			*/
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000	/* base address		*/
-#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 512M			*/
-#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
-#endif /* CONFIG_PCIE1 */
-
-/* NAND FLASH */
-#ifdef CONFIG_NAND
-
-#define CONFIG_NAND_FSL_UPM	1
-
-#define	CONFIG_MTD_NAND_ECC_JFFS2	1	/* use JFFS2 ECC	*/
-
-/* address distance between chip selects */
-#define	CONFIG_SYS_NAND_SELECT_DEVICE	1
-#define	CONFIG_SYS_NAND_CS_DIST	0x200
-
-#define CONFIG_SYS_NAND_SIZE		0x8000
-#define CONFIG_SYS_NAND_BASE		(CONFIG_SYS_CCSRBAR + 0x03010000)
-
-#define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND devices	*/
-#define CONFIG_SYS_NAND_MAX_CHIPS	2	/* Number of chips per device	*/
-
-/* CS3 for NAND Flash */
-#define CONFIG_SYS_BR3_PRELIM		((CONFIG_SYS_NAND_BASE & BR_BA) | \
-					 BR_PS_8 | BR_MS_UPMB | BR_V)
-#define CONFIG_SYS_OR3_PRELIM		(P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | OR_UPM_BI)
-
-#define NAND_BIG_DELAY_US		25	/* max tR for Samsung devices	*/
-
-#endif /* CONFIG_NAND */
-
-/*
- * General PCI
- * Addresses are mapped 1-1.
- */
-#define CONFIG_SYS_PCI1_MEM_BUS		0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BUS
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M			*/
-#define CONFIG_SYS_PCI1_IO_BUS	(CONFIG_SYS_CCSRBAR + 0x02000000)
-#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BUS
-#define CONFIG_SYS_PCI1_IO_SIZE	0x1000000	/*  16M			*/
-
-#ifdef CONFIG_PCIE1
-/*
- * General PCI express
- * Addresses are mapped 1-1.
- */
-#ifdef CONFIG_TQM_BIGFLASH
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xb0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000      /* 512M                 */
-#define CONFIG_SYS_PCIE1_IO_BUS		0xaf000000
-#else /* !CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
-#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000      /* 512M                 */
-#define CONFIG_SYS_PCIE1_IO_BUS		0xef000000
-#endif /* CONFIG_TQM_BIGFLASH */
-#define CONFIG_SYS_PCIE1_MEM_PHYS	CONFIG_SYS_PCIE1_MEM_BUS
-#define CONFIG_SYS_PCIE1_IO_PHYS	CONFIG_SYS_PCIE1_IO_BUS
-#define CONFIG_SYS_PCIE1_IO_SIZE	0x1000000       /* 16M                  */
-#endif /* CONFIG_PCIE1 */
-
-#if defined(CONFIG_PCI)
-
-#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
-
-#define CONFIG_EEPRO100
-#undef CONFIG_TULIP
-
-#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola			*/
-
-#endif /* CONFIG_PCI */
-
-
-#define CONFIG_MII		1	/* MII PHY management		*/
-#define CONFIG_TSEC1	1
-#define CONFIG_TSEC1_NAME	"TSEC0"
-#define CONFIG_TSEC2	1
-#define CONFIG_TSEC2_NAME	"TSEC1"
-#define TSEC1_PHY_ADDR		2
-#define TSEC2_PHY_ADDR		1
-#define TSEC1_PHYIDX		0
-#define TSEC2_PHYIDX		0
-#define TSEC1_FLAGS		TSEC_GIGABIT
-#define TSEC2_FLAGS		TSEC_GIGABIT
-#define FEC_PHY_ADDR		3
-#define FEC_PHYIDX		0
-#define FEC_FLAGS		0
-#define CONFIG_HAS_ETH0
-#define CONFIG_HAS_ETH1
-#define CONFIG_HAS_ETH2
-
-#ifdef CONFIG_TQM8548
-/*
- * TQM8548 has 4 ethernet ports. 4 ETSEC's.
- *
- * On the STK85xx Starterkit the ETSEC3/4 ports are on an
- * additional adapter (AIO) between module and Starterkit.
- */
-#define CONFIG_TSEC3	1
-#define CONFIG_TSEC3_NAME	"TSEC2"
-#define CONFIG_TSEC4	1
-#define CONFIG_TSEC4_NAME	"TSEC3"
-#define TSEC3_PHY_ADDR		4
-#define TSEC4_PHY_ADDR		5
-#define TSEC3_PHYIDX		0
-#define TSEC4_PHYIDX		0
-#define TSEC3_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define TSEC4_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
-#define CONFIG_HAS_ETH3
-#define CONFIG_HAS_ETH4
-#endif	/* CONFIG_TQM8548 */
-
-/* Options are TSEC[0-1], FEC */
-#define CONFIG_ETHPRIME		"TSEC0"
-
-#if defined(CONFIG_TQM8540)
-/*
- * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
- * The FEC port is connected on the same signals as the FCC3 port
- * of the TQM8560 to the baseboard (STK85xx Starterkit).
- *
- * On the STK85xx Starterkit the X47/X50 jumper has to be set to
- * a - d (X50.2 - 3) to enable the FEC port.
- */
-#define CONFIG_MPC85XX_FEC	1
-#define CONFIG_MPC85XX_FEC_NAME	"FEC"
-#endif
-
-#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
-/*
- * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
- * can be used at once, since only one FCC port is available on the STK85xx
- * Starterkit.
- *
- * To use this port you have to configure U-Boot to use the FCC port 1...2
- * and set the X47/X50 jumper to:
- * FCC1: a - b (X47.2 - X50.2)
- * FCC2: a - c (X50.2 - 1)
- */
-#define CONFIG_ETHER_ON_FCC
-#define	CONFIG_ETHER_INDEX    1	/* FCC channel for ethernet	*/
-#endif
-
-#if defined(CONFIG_TQM8560)
-/*
- * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
- * can be used at once, since only one FCC port is available on the STK85xx
- * Starterkit.
- *
- * To use this port you have to configure U-Boot to use the FCC port 1...3
- * and set the X47/X50 jumper to:
- * FCC1: a - b (X47.2 - X50.2)
- * FCC2: a - c (X50.2 - 1)
- * FCC3: a - d (X50.2 - 3)
- */
-#define CONFIG_ETHER_ON_FCC
-#define	CONFIG_ETHER_INDEX    3	/* FCC channel for ethernet	*/
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
-#define CONFIG_ETHER_ON_FCC1
-#define CONFIG_SYS_CMXFCR_MASK1	(CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \
-				 CMXFCR_TF1CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE1	(CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
-#define CONFIG_SYS_CPMFCR_RAMTYPE	0
-#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
-#define CONFIG_ETHER_ON_FCC2
-#define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \
-				 CMXFCR_TF2CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
-#define CONFIG_SYS_CPMFCR_RAMTYPE	0
-#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif
-
-#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
-#define CONFIG_ETHER_ON_FCC3
-#define CONFIG_SYS_CMXFCR_MASK3	(CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \
-				 CMXFCR_TF3CS_MSK)
-#define CONFIG_SYS_CMXFCR_VALUE3	(CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
-#define CONFIG_SYS_CPMFCR_RAMTYPE	0
-#define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE | FCC_PSMR_LPB)
-#endif
-
-/*
- * Environment
- */
-#define CONFIG_ENV_IS_IN_FLASH	1
-
-#define CONFIG_ENV_SECT_SIZE	0x40000 /* 256K (one sector) for env	*/
-#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
-
-#define	CONFIG_TIMESTAMP	/* Print image info with ts	*/
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-#ifdef CONFIG_NAND
-/*
- * Use NAND-FLash as JFFS2 device
- */
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_JFFS2
-
-#define	CONFIG_JFFS2_NAND	1
-
-#ifdef CONFIG_CMD_MTDPARTS
-#define CONFIG_MTD_DEVICE		/* needed for mtdparts commands */
-#define CONFIG_FLASH_CFI_MTD
-#define MTDIDS_DEFAULT		"nand0=TQM85xx-nand"
-#define MTDPARTS_DEFAULT	"mtdparts=TQM85xx-nand:-"
-#else
-#define CONFIG_JFFS2_DEV 	"nand0"	/* NAND device jffs2 lives on	*/
-#define CONFIG_JFFS2_PART_OFFSET 0	/* start of jffs2 partition	*/
-#define CONFIG_JFFS2_PART_SIZE	0x200000 /* size of jffs2 partition	*/
-#endif /* CONFIG_CMD_MTDPARTS */
-
-#endif /* CONFIG_NAND */
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_NFS
-#define CONFIG_CMD_SNTP
-#ifndef CONFIG_TQM8548_AG
-#define CONFIG_CMD_DATE
-#endif
-#define CONFIG_CMD_EEPROM
-#define CONFIG_CMD_DTT
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_REGINFO
-
-#if defined(CONFIG_PCI)
-#define CONFIG_CMD_PCI
-#endif
-
-#undef CONFIG_WATCHDOG			/* watchdog disabled		*/
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
-#else
-#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
-#endif
-
-#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE + \
-			 sizeof(CONFIG_SYS_PROMPT) + 16)   /* Print Buf Size	*/
-#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
-#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
-#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks	*/
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux	*/
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port*/
-#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use	*/
-#endif
-
-#define CONFIG_LOADADDR	 200000		/* default addr for tftp & bootm*/
-
-#define CONFIG_BOOTDELAY 5		/* -1 disables auto-boot	*/
-
-#define CONFIG_PREBOOT	"echo;"	\
-	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
-	"echo"
-
-#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/
-
-
-/*
- * Setup some board specific values for the default environment variables
- */
-#ifdef CONFIG_CPM2
-#define CONFIG_ENV_CONSDEV		"consdev=ttyCPM0\0"
-#else
-#define CONFIG_ENV_CONSDEV		"consdev=ttyS0\0"
-#endif
-#define CONFIG_ENV_FDT_FILE	"fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \
-				MK_STR(CONFIG_HOSTNAME)".dtb\0"
-#define CONFIG_ENV_BOOTFILE	"bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0"
-#define CONFIG_ENV_UBOOT		"uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \
-				"uboot_addr="MK_STR(CONFIG_SYS_TEXT_BASE)"\0"
-
-#define	CONFIG_EXTRA_ENV_SETTINGS					\
-	CONFIG_ENV_BOOTFILE						\
-	CONFIG_ENV_FDT_FILE						\
-	CONFIG_ENV_CONSDEV						\
-	"netdev=eth0\0"							\
-	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
-		"nfsroot=$serverip:$rootpath\0"				\
-	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
-	"addip=setenv bootargs $bootargs "				\
-		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
-		":$hostname:$netdev:off panic=1\0"			\
-	"addcons=setenv bootargs $bootargs "				\
-		"console=$consdev,$baudrate\0"				\
-	"flash_nfs=run nfsargs addip addcons;"				\
-		"bootm $kernel_addr - $fdt_addr\0"			\
-	"flash_self=run ramargs addip addcons;"				\
-		"bootm $kernel_addr $ramdisk_addr $fdt_addr\0"		\
-	"net_nfs=tftp $kernel_addr_r $bootfile;"       			\
-		"tftp $fdt_addr_r $fdt_file;"				\
-		"run nfsargs addip addcons;"				\
-		"bootm $kernel_addr_r - $fdt_addr_r\0"    		\
-	"rootpath=/opt/eldk/ppc_85xx\0"					\
-	"fdt_addr_r=900000\0"						\
-	"kernel_addr_r=1000000\0"      					\
-	"fdt_addr=ffec0000\0"						\
-	"kernel_addr=ffd00000\0"					\
-	"ramdisk_addr=ff800000\0"					\
-	CONFIG_ENV_UBOOT						\
-	"load=tftp 100000 $uboot\0"					\
-	"update=protect off $uboot_addr +$filesize;"			\
-		"erase $uboot_addr +$filesize;"				\
-		"cp.b 100000 $uboot_addr $filesize"			\
-	"upd=run load update\0"						\
-	""
-#define CONFIG_BOOTCOMMAND	"run flash_self"
-
-#endif /* __CONFIG_H */