diff mbox

[U-Boot,u-boot] Adding missing CONFIG_SYS_CACHELINE_SIZE to boards definitions

Message ID 506D48C0.4040407@bus-elektronik.de
State Changes Requested
Delegated to: Albert ARIBAUD
Headers show

Commit Message

esw@bus-elektronik.de Oct. 4, 2012, 8:28 a.m. UTC
Dear Lukasz,

> Hi Jens and Helmut,
> 
>> On Thu, Aug 23, 2012 at 10:13:13PM -0000, Lukasz Majewski wrote:
>>
>>> The restoration of GPT table (both primary and secondary) is now
>>> possible. Simple GUID generation is supported.
>>>
>>> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
>>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
>>
>> While the changes are fine, tt01 and eb_cpux9k2 use CONFIG_PART_EFI
>> and do not set CONFIG_SYS_CACHELINE_SIZE and so fail to build after
>> this patch.  tt01 is easily fixable (it relies on a non-exported
>> define elsewhere to 32) but the eb_cpu9k2 please contact the listed
>> board maintainer to get the define added.
>>
> 
> Would it be possible to add the CONFIG_SYS_CACHELINE_SIZE
> definition to ./include/configs/{tty01|eb_cpux9k2} boards definition?
> 
The eb_cpux9k2 board based on at91rm9200 soc. This soc has currently no cache implementation. So I think your run in this error.

The attached patch sets the define to the soc default.

We can also set #define CONFIG_SYS_DCACHE_OFF

regards Jens

Comments

Albert ARIBAUD Oct. 18, 2012, 6:48 p.m. UTC | #1
Hi esw,

(resending as it was erroneously posted on gmane; sorry for any dupes)

On Thu, 4 Oct 2012 10:28:48 +0200, esw <esw@bus-elektronik.de> wrote:

> Dear Lukasz,
> 
> > Hi Jens and Helmut,
> > 
> >> On Thu, Aug 23, 2012 at 10:13:13PM -0000, Lukasz Majewski wrote:
> >>
> >>> The restoration of GPT table (both primary and secondary) is now
> >>> possible. Simple GUID generation is supported.
> >>>
> >>> Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
> >>> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
> >>
> >> While the changes are fine, tt01 and eb_cpux9k2 use CONFIG_PART_EFI
> >> and do not set CONFIG_SYS_CACHELINE_SIZE and so fail to build after
> >> this patch.  tt01 is easily fixable (it relies on a non-exported
> >> define elsewhere to 32) but the eb_cpu9k2 please contact the listed
> >> board maintainer to get the define added.
> >>
> > 
> > Would it be possible to add the CONFIG_SYS_CACHELINE_SIZE
> > definition to ./include/configs/{tty01|eb_cpux9k2} boards definition?
> > 
> The eb_cpux9k2 board based on at91rm9200 soc. This soc has currently no cache implementation. So I think your run in this error.
> 
> The attached patch sets the define to the soc default.
> 
> We can also set #define CONFIG_SYS_DCACHE_OFF
> 
> regards Jens

If this is to be considered an actual patch submission, then please
submit via git format-patch/git send-email or patman, and copy the at91
custodian. This patch has been marked as "changes requested" in PW.

Amicalement,
diff mbox

Patch

From fe0e5e6d93e7f709fb058e7c3e551fca20191ddb Mon Sep 17 00:00:00 2001
From: "Jens Scharsig (BuS Elektronik)" <esw@bus-elektronik.de>
Date: Thu, 4 Oct 2012 10:11:38 +0200
Subject: [PATCH 2/2] * add CONFIG_SYS_CACLELINE_SIZE to eb_cpux9k2 board
Cc: esw@bus-elektronik.de, js_at_ng@scharsoft.de


Signed-off-by: Jens Scharsig (BuS Elektronik) <esw@bus-elektronik.de>
---
 include/configs/eb_cpux9k2.h |    4 +++-
 1 Datei geändert, 3 Zeilen hinzugefügt(+), 1 Zeile entfernt(-)

diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h
index 9371ec3..6dcd605 100644
--- a/include/configs/eb_cpux9k2.h
+++ b/include/configs/eb_cpux9k2.h
@@ -43,6 +43,9 @@ 
 
 #define MACH_TYPE_EB_CPUX9K2		1977
 #define CONFIG_MACH_TYPE		MACH_TYPE_EB_CPUX9K2
+
+#define CONFIG_SYS_CACHELINE_SIZE	32
+
 /*--------------------------------------------------------------------------*/
 #ifndef CONFIG_RAMBOOT
 #define CONFIG_SYS_TEXT_BASE		0x00000000
@@ -56,7 +59,6 @@ 
 #define CONFIG_SYS_U_BOOT_BASE		PHYS_FLASH_1
 #define CONFIG_SYS_U_BOOT_SIZE		0x60000 /* 384 KBytes */
 
-
 #define CONFIG_BOOT_RETRY_TIME		30
 #define CONFIG_CMDLINE_EDITING
 
-- 
1.7.10.4