Patchwork [U-Boot,V3,27/32] mx6qsabrelite: add support for mx6 solo/duallite

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Submitter Troy Kisky
Date Oct. 4, 2012, 1:47 a.m.
Message ID <1349315254-21151-28-git-send-email-troy.kisky@boundarydevices.com>
Download mbox | patch
Permalink /patch/189013/
State Changes Requested
Delegated to: Stefano Babic
Headers show

Comments

Troy Kisky - Oct. 4, 2012, 1:47 a.m.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
 board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235 ++++++-------------------
 board/freescale/mx6qsabrelite/pads.h          |  172 ++++++++++++++++++
 2 files changed, 229 insertions(+), 178 deletions(-)
 create mode 100644 board/freescale/mx6qsabrelite/pads.h
Otavio Salvador - Oct. 4, 2012, 3:23 a.m.
On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
<troy.kisky@boundarydevices.com> wrote:
> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
> ---
>  board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235 ++++++-------------------
>  board/freescale/mx6qsabrelite/pads.h          |  172 ++++++++++++++++++

I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not confusing.
Troy Kisky - Oct. 4, 2012, 11:34 p.m.
On 10/3/2012 8:23 PM, Otavio Salvador wrote:
> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
> <troy.kisky@boundarydevices.com> wrote:
>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>> ---
>>   board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235 ++++++-------------------
>>   board/freescale/mx6qsabrelite/pads.h          |  172 ++++++++++++++++++
> I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not confusing.
>
Both mx6qsabrelite.c and mx6qsabrelite.h should be renamed to drop the q.
Also, the directory could be renamed ?
I think a follow on patch later to reduced conflicts with others work 
would be
appropriate.

Troy
Stefano Babic - Oct. 8, 2012, 1:47 p.m.
On 05/10/2012 01:34, Troy Kisky wrote:
> On 10/3/2012 8:23 PM, Otavio Salvador wrote:
>> On Wed, Oct 3, 2012 at 10:47 PM, Troy Kisky
>> <troy.kisky@boundarydevices.com> wrote:
>>> Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
>>> ---
>>>   board/freescale/mx6qsabrelite/mx6qsabrelite.c |  235
>>> ++++++-------------------
>>>   board/freescale/mx6qsabrelite/pads.h          |  172
>>> ++++++++++++++++++
>> I'd say mx6qsabrelite could be renamed to mx6sabrelite so it is not
>> confusing.
>>
> Both mx6qsabrelite.c and mx6qsabrelite.h should be renamed to drop the q.
> Also, the directory could be renamed ?

Yes, it can, but add board's maintainer (Fabio) to the discussion.

Regards,
Stefano

Patch

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 4b4e89b..454972c 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -26,6 +26,8 @@ 
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6x_pins.h>
+#include <asm/arch/mx6dl_pins.h>
+#include <asm/arch/sys_proto.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
@@ -38,162 +40,52 @@ 
 #include <netdev.h>
 DECLARE_GLOBAL_DATA_PTR;
 
-#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
-       PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
-       PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
-       PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
-       PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
-
-#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
-
-#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
-	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
-
-#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
-	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
-
-#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
-	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
-	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
-	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+#ifdef CONFIG_MX6Q
+#include "pads.h"
+#endif
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#define FOR_DL_SOLO
+#include "pads.h"
+#endif
 
-int dram_init(void)
+int cpu_is_mx6q(void)
 {
-       gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
-
-       return 0;
+	return (get_cpu_rev() >> 12) == MXC_CPU_MX6Q;
 }
 
-iomux_v3_cfg_t uart1_pads[] = {
-	MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-	MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-iomux_v3_cfg_t uart2_pads[] = {
-       MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-       MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
-};
-
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-
-/* I2C1, SGTL5000 */
-struct i2c_pads_info i2c_pad_info0 = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
-		.gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
-		.gp = IMX_GPIO_NR(3, 21)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
-		.gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
-		.gp = IMX_GPIO_NR(3, 28)
-	}
-};
-
-/* I2C2 Camera, MIPI */
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
-		.gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
-		.gp = IMX_GPIO_NR(4, 12)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
-		.gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
-		.gp = IMX_GPIO_NR(4, 13)
-	}
-};
-
-/* I2C3, J15 - RGB connector */
-struct i2c_pads_info i2c_pad_info2 = {
-	.scl = {
-		.i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
-		.gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
-		.gp = IMX_GPIO_NR(1, 5)
-	},
-	.sda = {
-		.i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
-		.gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
-		.gp = IMX_GPIO_NR(7, 11)
-	}
-};
+#if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
+#ifdef CONFIG_MX6Q
+#define GET_MX6_REF(ref) (cpu_is_mx6q() ? mx6q_##ref : mx6dl_solo_##ref)
+#define IOMUX_SETUP(list)  iomux_setup(mx6q_##list, ARRAY_SIZE(mx6q_##list), \
+		mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
 
-iomux_v3_cfg_t usdhc3_pads[] = {
-       MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
+int iomux_setup(iomux_v3_cfg_t *mx6q_pad_list, int mx6q_pad_cnt,
+		iomux_v3_cfg_t *mx6dl_solo_pad_list, int mx6dl_solo_pad_cnt)
+{
+	int mx6q = cpu_is_mx6q();
+	iomux_v3_cfg_t *p =  mx6q ? mx6q_pad_list : mx6dl_solo_pad_list;
+	int cnt = mx6q ? mx6q_pad_cnt : mx6dl_solo_pad_cnt;
 
-iomux_v3_cfg_t usdhc4_pads[] = {
-       MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
-       MX6Q_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
-};
+	return imx_iomux_v3_setup_multiple_pads(p, cnt);
+}
 
-iomux_v3_cfg_t enet_pads1[] = {
-	MX6Q_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	/* pin 35 - 1 (PHY_AD2) on reset */
-	MX6Q_PAD_RGMII_RXC__GPIO_6_30		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 32 - 1 - (MODE0) all */
-	MX6Q_PAD_RGMII_RD0__GPIO_6_25		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 31 - 1 - (MODE1) all */
-	MX6Q_PAD_RGMII_RD1__GPIO_6_27		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 28 - 1 - (MODE2) all */
-	MX6Q_PAD_RGMII_RD2__GPIO_6_28		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 27 - 1 - (MODE3) all */
-	MX6Q_PAD_RGMII_RD3__GPIO_6_29		| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
-	MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24	| MUX_PAD_CTRL(NO_PAD_CTRL),
-	/* pin 42 PHY nRST */
-	MX6Q_PAD_EIM_D23__GPIO_3_23		| MUX_PAD_CTRL(NO_PAD_CTRL),
-};
+#else
+#define GET_MX6_REF(ref) (mx6dl_solo_##ref)
+#define IOMUX_SETUP(list)  imx_iomux_v3_setup_multiple_pads(	\
+		mx6dl_solo_##list, ARRAY_SIZE(mx6dl_solo_##list))
+#endif
+#else
 
-iomux_v3_cfg_t enet_pads2[] = {
-	MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-	MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
-};
+#define GET_MX6_REF(ref) (mx6q_##ref)
+#define IOMUX_SETUP(list)  imx_iomux_v3_setup_multiple_pads(	\
+		mx6q_##list, ARRAY_SIZE(mx6q_##list))
+#endif
 
-/* Button assignments for J14 */
-static iomux_v3_cfg_t button_pads[] = {
-	/* Menu */
-	MX6Q_PAD_NANDF_D1__GPIO_2_1	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Back */
-	MX6Q_PAD_NANDF_D2__GPIO_2_2	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Labelled Search (mapped to Power under Android) */
-	MX6Q_PAD_NANDF_D3__GPIO_2_3	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Home */
-	MX6Q_PAD_NANDF_D4__GPIO_2_4	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Volume Down */
-	MX6Q_PAD_GPIO_19__GPIO_4_5	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-	/* Volume Up */
-	MX6Q_PAD_GPIO_18__GPIO_7_13	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
-};
+int dram_init(void)
+{
+	gd->ram_size = imx_ddr_size();
+	return 0;
+}
 
 static void setup_iomux_enet(void)
 {
@@ -203,30 +95,26 @@  static void setup_iomux_enet(void)
 	gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 	gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 	gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
-	imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
+	IOMUX_SETUP(enet_pads1);
 	gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 
 	/* Need delay 10ms according to KSZ9021 spec */
 	udelay(1000 * 10);
 	gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 
-	imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
+	IOMUX_SETUP(enet_pads2);
 }
 
-iomux_v3_cfg_t usb_pads[] = {
-	MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
-};
-
 static void setup_iomux_uart(void)
 {
-	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
-       imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
+	IOMUX_SETUP(uart1_pads);
+	IOMUX_SETUP(uart2_pads);
 }
 
 #ifdef CONFIG_USB_EHCI_MX6
 int board_ehci_hcd_init(int port)
 {
-	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
+	IOMUX_SETUP(usb_pads);
 
 	/* Reset USB hub */
 	gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
@@ -267,12 +155,10 @@  int board_mmc_init(bd_t *bis)
        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 	       switch (index) {
 	       case 0:
-		       imx_iomux_v3_setup_multiple_pads(
-			       usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
+		       IOMUX_SETUP(usdhc3_pads);
 		       break;
 	       case 1:
-		       imx_iomux_v3_setup_multiple_pads(
-			       usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
+		       IOMUX_SETUP(usdhc4_pads);
 		       break;
 	       default:
 		       printf("Warning: you configured more USDHC controllers"
@@ -294,19 +180,10 @@  u32 get_board_rev(void)
 }
 
 #ifdef CONFIG_MXC_SPI
-iomux_v3_cfg_t ecspi1_pads[] = {
-	/* SS1 */
-	MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
-	MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
-};
-
 void setup_spi(void)
 {
 	gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
-	imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
-					 ARRAY_SIZE(ecspi1_pads));
+	IOMUX_SETUP(ecspi1_pads);
 }
 #endif
 
@@ -342,8 +219,7 @@  int board_eth_init(bd_t *bis)
 
 static void setup_buttons(void)
 {
-	imx_iomux_v3_setup_multiple_pads(button_pads,
-					 ARRAY_SIZE(button_pads));
+	IOMUX_SETUP(button_pads);
 }
 
 #ifdef CONFIG_CMD_SATA
@@ -382,15 +258,17 @@  int board_early_init_f(void)
 
 int board_init(void)
 {
+	struct i2c_pads_info *p = GET_MX6_REF(i2c_pad_info);
+
        /* address of boot parameters */
        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 
 #ifdef CONFIG_MXC_SPI
 	setup_spi();
 #endif
-	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
-	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
-	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
+	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &p[0]);
+	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &p[1]);
+	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &p[2]);
 
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
@@ -401,9 +279,10 @@  int board_init(void)
 
 int checkboard(void)
 {
-       puts("Board: MX6Q-Sabre Lite\n");
-
-       return 0;
+	puts("Board: MX");
+	puts(get_imx_type(get_cpu_rev() >> 12));
+	puts("-Sabre Lite\n");
+	return 0;
 }
 
 struct button_key {
diff --git a/board/freescale/mx6qsabrelite/pads.h b/board/freescale/mx6qsabrelite/pads.h
new file mode 100644
index 0000000..e7ffe21
--- /dev/null
+++ b/board/freescale/mx6qsabrelite/pads.h
@@ -0,0 +1,172 @@ 
+#undef MX6PAD
+#undef MX6NAME
+
+#ifdef FOR_DL_SOLO
+#define MX6PAD(a) MX6DL_PAD_##a
+#define MX6NAME(a) mx6dl_solo_##a
+#else
+#define MX6PAD(a) MX6Q_PAD_##a
+#define MX6NAME(a) mx6q_##a
+#endif
+
+#define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	       \
+	PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |	       \
+	PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |	       \
+	PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
+
+#define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED	  |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define SPI_PAD_CTRL (PAD_CTL_HYS |				\
+	PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
+
+#define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |		\
+	PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
+
+#define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
+	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
+	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
+	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
+
+iomux_v3_cfg_t MX6NAME(uart1_pads)[] = {
+	MX6PAD(SD3_DAT6__UART1_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6PAD(SD3_DAT7__UART1_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(uart2_pads)[] = {
+	MX6PAD(EIM_D26__UART2_TXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+	MX6PAD(EIM_D27__UART2_RXD) | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
+
+struct i2c_pads_info MX6NAME(i2c_pad_info)[] = {
+	{
+		/* I2C1, SGTL5000 */
+		.scl = {
+			.i2c_mode = MX6PAD(EIM_D21__I2C1_SCL) | PC,
+			.gpio_mode = MX6PAD(EIM_D21__GPIO_3_21) | PC,
+			.gp = IMX_GPIO_NR(3, 21)
+		},
+		.sda = {
+			.i2c_mode = MX6PAD(EIM_D28__I2C1_SDA) | PC,
+			.gpio_mode = MX6PAD(EIM_D28__GPIO_3_28) | PC,
+			.gp = IMX_GPIO_NR(3, 28)
+		}
+	}, {
+		/* I2C2 Camera, MIPI */
+		.scl = {
+			.i2c_mode = MX6PAD(KEY_COL3__I2C2_SCL) | PC,
+			.gpio_mode = MX6PAD(KEY_COL3__GPIO_4_12) | PC,
+			.gp = IMX_GPIO_NR(4, 12)
+		},
+		.sda = {
+			.i2c_mode = MX6PAD(KEY_ROW3__I2C2_SDA) | PC,
+			.gpio_mode = MX6PAD(KEY_ROW3__GPIO_4_13) | PC,
+			.gp = IMX_GPIO_NR(4, 13)
+		}
+	}, {
+		/* I2C3, J15 - RGB connector */
+		.scl = {
+			.i2c_mode = MX6PAD(GPIO_5__I2C3_SCL) | PC,
+			.gpio_mode = MX6PAD(GPIO_5__GPIO_1_5) | PC,
+			.gp = IMX_GPIO_NR(1, 5)
+		},
+		.sda = {
+			.i2c_mode = MX6PAD(GPIO_16__I2C3_SDA) | PC,
+			.gpio_mode = MX6PAD(GPIO_16__GPIO_7_11) | PC,
+			.gp = IMX_GPIO_NR(7, 11)
+		}
+	}
+};
+
+iomux_v3_cfg_t MX6NAME(usdhc3_pads)[] = {
+	MX6PAD(SD3_CLK__USDHC3_CLK)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_CMD__USDHC3_CMD)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT0__USDHC3_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT1__USDHC3_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT2__USDHC3_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT3__USDHC3_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD3_DAT5__GPIO_7_0)    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t MX6NAME(usdhc4_pads)[] = {
+	MX6PAD(SD4_CLK__USDHC4_CLK)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_CMD__USDHC4_CMD)   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_DAT0__USDHC4_DAT0) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_DAT1__USDHC4_DAT1) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_DAT2__USDHC4_DAT2) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(SD4_DAT3__USDHC4_DAT3) | MUX_PAD_CTRL(USDHC_PAD_CTRL),
+	MX6PAD(NANDF_D6__GPIO_2_6)    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
+};
+
+iomux_v3_cfg_t MX6NAME(enet_pads1)[] = {
+	MX6PAD(ENET_MDIO__ENET_MDIO)		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(ENET_MDC__ENET_MDC)		| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TXC__ENET_RGMII_TXC)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TD0__ENET_RGMII_TD0)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TD1__ENET_RGMII_TD1)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TD2__ENET_RGMII_TD2)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TD3__ENET_RGMII_TD3)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_TX_CTL__RGMII_TX_CTL)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(ENET_REF_CLK__ENET_TX_CLK)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	/* pin 35 - 1 (PHY_AD2) on reset */
+	MX6PAD(RGMII_RXC__GPIO_6_30)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 32 - 1 - (MODE0) all */
+	MX6PAD(RGMII_RD0__GPIO_6_25)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 31 - 1 - (MODE1) all */
+	MX6PAD(RGMII_RD1__GPIO_6_27)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 28 - 1 - (MODE2) all */
+	MX6PAD(RGMII_RD2__GPIO_6_28)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 27 - 1 - (MODE3) all */
+	MX6PAD(RGMII_RD3__GPIO_6_29)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
+	MX6PAD(RGMII_RX_CTL__GPIO_6_24)	| MUX_PAD_CTRL(NO_PAD_CTRL),
+	/* pin 42 PHY nRST */
+	MX6PAD(EIM_D23__GPIO_3_23)		| MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(enet_pads2)[] = {
+	MX6PAD(RGMII_RXC__ENET_RGMII_RXC)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RD0__ENET_RGMII_RD0)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RD1__ENET_RGMII_RD1)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RD2__ENET_RGMII_RD2)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RD3__ENET_RGMII_RD3)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+	MX6PAD(RGMII_RX_CTL__RGMII_RX_CTL)	| MUX_PAD_CTRL(ENET_PAD_CTRL),
+};
+
+/* Button assignments for J14 */
+static iomux_v3_cfg_t MX6NAME(button_pads)[] = {
+	/* Menu */
+	MX6PAD(NANDF_D1__GPIO_2_1)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Back */
+	MX6PAD(NANDF_D2__GPIO_2_2)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Labelled Search (mapped to Power under Android) */
+	MX6PAD(NANDF_D3__GPIO_2_3)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Home */
+	MX6PAD(NANDF_D4__GPIO_2_4)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Volume Down */
+	MX6PAD(GPIO_19__GPIO_4_5)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+	/* Volume Up */
+	MX6PAD(GPIO_18__GPIO_7_13)	| MUX_PAD_CTRL(BUTTON_PAD_CTRL),
+};
+
+iomux_v3_cfg_t MX6NAME(usb_pads)[] = {
+	MX6PAD(GPIO_17__GPIO_7_12) | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
+
+#ifdef CONFIG_MXC_SPI
+iomux_v3_cfg_t MX6NAME(ecspi1_pads)[] = {
+	/* SS1 */
+	MX6PAD(EIM_D19__GPIO_3_19)   | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6PAD(EIM_D17__ECSPI1_MISO) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6PAD(EIM_D18__ECSPI1_MOSI) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+	MX6PAD(EIM_D16__ECSPI1_SCLK) | MUX_PAD_CTRL(SPI_PAD_CTRL),
+};
+#endif