From patchwork Thu Oct 4 01:47:30 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 189012 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id DE5082C0094 for ; Thu, 4 Oct 2012 11:58:41 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6EE0128412; Thu, 4 Oct 2012 03:58:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 790wgxx5guoc; Thu, 4 Oct 2012 03:58:31 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BB475283E3; Thu, 4 Oct 2012 03:58:07 +0200 (CEST) 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bh=jlv9/5XqwgjzyA9Oq48N9TUwAMc+Q5Y4dfqVlco444A=; b=dioJiytDIUpV+I9Wo3RkKrLDWMWS4OILNhkWEaRcJI1c77+XyxG6/n56ah7JFI3vHR 6tbotrg3p55QihC/JoryX9RHgPHk9konLOURIcKLs+ddPWcVkTzCrd8Cb6VHLQjjHTjS V4FPEV+Z9ILEDW9Ykzk+P22ieka+BGCWVng9a4Eub/VkJEook5Lf14+vK8Xd9YwW2WDT FRzwwa0p5pc5Qn4FR7beuuD7EY40Xzd55Mg/YIJgFXZsLc6q1d//zDhRlAQH/m3LCuNy +KJg2e9JcIyQWK2l79pI1GNPq0R7Bco7iYl29wVf4xBvoqxGCHCxrC3Oqk0gBVlAGpCL 9bpA== Received: by 10.66.90.36 with SMTP id bt4mr9348241pab.54.1349315859407; Wed, 03 Oct 2012 18:57:39 -0700 (PDT) Received: from officeserver-2 ([70.96.116.236]) by mx.google.com with ESMTPS id c5sm3374818pay.5.2012.10.03.18.57.37 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 03 Oct 2012 18:57:38 -0700 (PDT) Received: from tkisky by officeserver-2 with local (Exim 4.76) (envelope-from ) id 1TJaXe-0005XS-I7; Wed, 03 Oct 2012 18:47:58 -0700 From: Troy Kisky To: sbabic@denx.de Date: Wed, 3 Oct 2012 18:47:30 -0700 Message-Id: <1349315254-21151-29-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349315254-21151-1-git-send-email-troy.kisky@boundarydevices.com> References: <1348281558-19520-1-git-send-email-troy.kisky@boundarydevices.com> <1349315254-21151-1-git-send-email-troy.kisky@boundarydevices.com> X-Gm-Message-State: ALoCoQk0kQZFP4+bl+rAdzE0DTmBqqRUJQ1DYJQY0SEkAlKYfpbbEuJPioOC3DxxySNbbHBjHtcT Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V3 28/32] mx6q_4x_mt41j128.cfg: add mx6 solo/duallite support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Troy Kisky --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 120 +++++++++++++++++++------- 1 file changed, 87 insertions(+), 33 deletions(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 9e20db0..f45f93e 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -49,6 +49,15 @@ BOOT_FROM sd * Address absolute address of the register * value value to be stored in the register */ +/* + * DDR3 settings + * MX6Q ddr is limited to 1066 Mhz, currently 1056 MHz(528 MHz clock), + * memory bus width: 64 bits, x16/x32/x64 + * MX6DL ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 64 bits, x16/x32/x64 + * MX6SOLO ddr is limited to 800 MHz(400 MHz clock) + * memory bus width: 32 bits, x16/x32 + */ WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030) WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030) WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030) @@ -90,6 +99,7 @@ WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030) WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030) WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030) + /* (differential input) */ WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000) /* disable ddr pullups */ @@ -119,48 +129,92 @@ WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740) * MDSCR, con_req */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000) + /* - * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks - * tXP=4 clocks, tXPDLL=13 clocks - * tFAW=24 clocks, cas=8 cycles + * MDCFG0, + * MX6Q: + * tRFC=0x56 clocks, tXS=0x5b clocks, tXP=4 clocks, tXPDLL=13 clocks + * tFAW=24 clocks, cas=8 cycles + * MX6DL/SOLO: + * tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks + * tFAW=19 clocks, cas=6 cycles */ -WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975) +WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323) + /* - * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8 - * tMRD=4, tCWL=6 + * MDCFG1, + * MX6Q: + * tRDC=8, tRP=8, tRC=27, tRAS=20, tRPA=tRP+1, tWR=8, tMRD=4, tCWL=6 + * MX6DL/SOLO: + * tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5 */ -WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64) +WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63) + /* * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4 */ WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB) WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2) - WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21) -WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040) -WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576) /* - * Mx6Q - 64 bit wide ddr + * MMDC_MDOTC, + * MX6Q: + * tAOFPD=2 cycles, tAONPD=2, tANPD=5, tAXPD=5, tODTLon=5, tODT_idle_off=5 + * MX6DL/SOLO: + * tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4, tODT_idle_off=4 + */ +WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030) + +/* + * MDPDC - [17:16](2) => CKE pulse width = 3 cycles. + * [15:12](5) => PWDT_1 = 256 cycles + * [11:8](5) =>PWDR_0 = 256 cycles + * MX6Q: [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6 cycles + * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles + */ +WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D) + +/* + * MX6Q/DL - 64 bit wide ddr * last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) = * 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27 */ +/* + * MX6SOLO - 32 bit wide ddr + * last address is (1<<28 (base) + 1<<29 - 1) / (1<<25) = + * 1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17 + */ /* MDASP, CS0_END */ -WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027) +WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017) /* - * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit - * mx6q : row+col+bank+width=14+10+3+3=30 = 1G + * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8 + * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G + * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M */ -WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000) +WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000) -/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */ -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032) +/* + * LOAD MR2: MDSCR, con_req, CS0, A10 set - RZQ/2 + * MX6Q: A3 set(CAS Write=6) + * MX6DL/SOLO: (CAS Write=5) + */ +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032) /* LOAD MR3, CS0 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033) -/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */ -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031) -/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */ -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030) + +/* + * LOAD MR1, CS0 + * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7 + * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6 + */ +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031) + +/* LOAD MR0, CS0 A8 set: DLL Reset + * MX6Q: A6 set: CAS=8 A11 set: WR=8 + * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7 + */ +WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030) /* ZQ calibrate, CS0 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040) @@ -173,18 +227,18 @@ WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227) WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227) /* MPDGCTRL0/1 DQS GATE*/ -WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350) -WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359) -WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350) -WRITE_ENTRY1(MMDC_P1_MPDGCTRL1, 0x03650348) -WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B) -WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341) -WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933) -WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36) -WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F) -WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F) -WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044) -WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044) +WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231) +WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218) +WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231) +WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218) +WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49) +WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49) +WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035) +WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035) +WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C) +WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E) +WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C) +WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E) /* MPMUR0 - Complete calibration by forced measurement */ WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)