From patchwork Thu Oct 4 01:47:23 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot, V3, 21/32] mx6q_4x_mt41j128.cfg: skip initiailizing non-existent memory From: Troy Kisky X-Patchwork-Id: 189006 Message-Id: <1349315254-21151-22-git-send-email-troy.kisky@boundarydevices.com> To: sbabic@denx.de Cc: u-boot@lists.denx.de Date: Wed, 3 Oct 2012 18:47:23 -0700 Sabrelite does not have memory associated with CS1 Signed-off-by: Troy Kisky --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 5 ----- 1 file changed, 5 deletions(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 9c622c8..2d03ff7 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -155,20 +155,15 @@ WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000) /* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032) -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A) /* LOAD MR3, CS0 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033) -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B) /* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031) -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039) /* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030) -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038) /* ZQ calibrate, CS0 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040) -WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048) WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003) WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003)