Patchwork [U-Boot,V3,32/32] imx-mkimage.h: use base + offset syntax

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Submitter Troy Kisky
Date Oct. 4, 2012, 1:47 a.m.
Message ID <1349315254-21151-33-git-send-email-troy.kisky@boundarydevices.com>
Download mbox | patch
Permalink /patch/188998/
State Changes Requested
Delegated to: Stefano Babic
Headers show

Comments

Troy Kisky - Oct. 4, 2012, 1:47 a.m.
Now that expression work, we can delete
the redundant MMC_P1_xxx defines and
just define MMC_P0 and MMC_P1 bases.

The other addresses are changed to a base
+ offset syntax as well.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
 arch/arm/include/asm/arch-mx6/imx-mkimage.h  |  205 ++++++++++++--------------
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |   90 +++++------
 2 files changed, 136 insertions(+), 159 deletions(-)

Patch

diff --git a/arch/arm/include/asm/arch-mx6/imx-mkimage.h b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
index 4abd3f1..dc9dadf 100644
--- a/arch/arm/include/asm/arch-mx6/imx-mkimage.h
+++ b/arch/arm/include/asm/arch-mx6/imx-mkimage.h
@@ -6,124 +6,101 @@ 
 #ifndef __ASM_ARCH_IMX_MKIMAGE_H__
 #define __ASM_ARCH_IMX_MKIMAGE_H__
 
-#define IOMUXC_GPR4		0x020e0010
-#define IOMUXC_GPR6		0x020e0018
-#define IOMUXC_GPR7		0x020e001c
-
-/* mx6 duallite and solo have same offsets */
+#define IRAM_FREE_START		0x00907000
+#define MMDC_P0			0x021b0000
+#define MMDC_P1			0x021b4000
+#define IOMUXC_BASE		0x020e0000
+#define CCM_BASE		0x020c4000
 
-#define IOM_DRAM_DQM0		MA(0x020e05ac, 0x020e0470, 0x0)
-#define IOM_DRAM_DQM1		MA(0x020e05b4, 0x020e0474, 0x0)
-#define IOM_DRAM_DQM2		MA(0x020e0528, 0x020e0478, 0x0)
-#define IOM_DRAM_DQM3		MA(0x020e0520, 0x020e047c, 0x0)
-#define IOM_DRAM_DQM4		MA(0x020e0514, 0x020e0480, 0x0)
-#define IOM_DRAM_DQM5		MA(0x020e0510, 0x020e0484, 0x0)
-#define IOM_DRAM_DQM6		MA(0x020e05bc, 0x020e0488, 0x0)
-#define IOM_DRAM_DQM7		MA(0x020e05c4, 0x020e048c, 0x0)
-
-#define IOM_DRAM_CAS		MA(0x020e056c, 0x020e0464, 0x0)
-#define IOM_DRAM_RAS		MA(0x020e0578, 0x020e0490, 0x0)
-#define IOM_DRAM_RESET		MA(0x020e057c, 0x020e0494, 0x0)
-#define IOM_DRAM_SDCLK_0	MA(0x020e0588, 0x020e04ac, 0x0)
-#define IOM_DRAM_SDCLK_1	MA(0x020e0594, 0x020e04b0, 0x0)
-#define IOM_DRAM_SDBA2		MA(0x020e058c, 0x020e04a0, 0x0)
-#define IOM_DRAM_SDCKE0		MA(0x020e0590, 0x020e04a4, 0x0)
-#define IOM_DRAM_SDCKE1		MA(0x020e0598, 0x020e04a8, 0x0)
-#define IOM_DRAM_SDODT0		MA(0x020e059c, 0x020e04b4, 0x0)
-#define IOM_DRAM_SDODT1		MA(0x020e05a0, 0x020e04b8, 0x0)
-
-#define IOM_DRAM_SDQS0		MA(0x020e05a8, 0x020e04bc, 0x0)
-#define IOM_DRAM_SDQS1		MA(0x020e05b0, 0x020e04c0, 0x0)
-#define IOM_DRAM_SDQS2		MA(0x020e0524, 0x020e04c4, 0x0)
-#define IOM_DRAM_SDQS3		MA(0x020e051c, 0x020e04c8, 0x0)
-#define IOM_DRAM_SDQS4		MA(0x020e0518, 0x020e04cc, 0x0)
-#define IOM_DRAM_SDQS5		MA(0x020e050c, 0x020e04d0, 0x0)
-#define IOM_DRAM_SDQS6		MA(0x020e05b8, 0x020e04d4, 0x0)
-#define IOM_DRAM_SDQS7		MA(0x020e05c0, 0x020e04d8, 0x0)
-
-#define IOM_GRP_B0DS		MA(0x020e0784, 0x020e0764, 0x0)
-#define IOM_GRP_B1DS		MA(0x020e0788, 0x020e0770, 0x0)
-#define IOM_GRP_B2DS		MA(0x020e0794, 0x020e0778, 0x0)
-#define IOM_GRP_B3DS		MA(0x020e079c, 0x020e077c, 0x0)
-#define IOM_GRP_B4DS		MA(0x020e07a0, 0x020e0780, 0x0)
-#define IOM_GRP_B5DS		MA(0x020e07a4, 0x020e0784, 0x0)
-#define IOM_GRP_B6DS		MA(0x020e07a8, 0x020e078c, 0x0)
-#define IOM_GRP_B7DS		MA(0x020e0748, 0x020e0748, 0x0)
-#define IOM_GRP_ADDDS		MA(0x020e074c, 0x020e074c, 0x0)
-#define IOM_DDRMODE_CTL		MA(0x020e0750, 0x020e0750, 0x0)
-#define IOM_GRP_DDRPKE		MA(0x020e0758, 0x020e0754, 0x0)
-#define IOM_GRP_DDRMODE		MA(0x020e0774, 0x020e0760, 0x0)
-#define IOM_GRP_CTLDS		MA(0x020e078c, 0x020e076c, 0x0)
-#define IOM_GRP_DDR_TYPE	MA(0x020e0798, 0x020e0774, 0x0)
+#define IOMUXC_GPR4		(IOMUXC_BASE + 0x010)
+#define IOMUXC_GPR6		(IOMUXC_BASE + 0x018)
+#define IOMUXC_GPR7		(IOMUXC_BASE + 0x01c)
 
-#define IRAM_FREE_START		0x00907000
+/* mx6 duallite and solo have same offsets */
 
-#define MMDC_P0_MDCTL		0x021b0000
-#define MMDC_P0_MDPDC		0x021b0004
-#define MMDC_P0_MDOTC		0x021b0008
-#define MMDC_P0_MDCFG0		0x021b000c
-#define MMDC_P0_MDCFG1		0x021b0010
-#define MMDC_P0_MDCFG2		0x021b0014
-#define MMDC_P0_MDMISC		0x021b0018
-#define MMDC_P0_MDSCR		0x021b001c
-#define MMDC_P0_MDREF		0x021b0020
-#define MMDC_P0_MDRWD		0x021b002c
-#define MMDC_P0_MDOR		0x021b0030
-#define MMDC_P0_MDASP		0x021b0040
-#define MMDC_P0_MAPSR		0x021b0404
-#define MMDC_P0_MPZQHWCTRL	0x021b0800
-#define MMDC_P0_MPWLDECTRL0	0x021b080c
-#define MMDC_P0_MPWLDECTRL1	0x021b0810
-#define MMDC_P0_MPODTCTRL	0x021b0818
-#define MMDC_P0_MPRDDQBY0DL	0x021b081c
-#define MMDC_P0_MPRDDQBY1DL	0x021b0820
-#define MMDC_P0_MPRDDQBY2DL	0x021b0824
-#define MMDC_P0_MPRDDQBY3DL	0x021b0828
-#define MMDC_P0_MPDGCTRL0	0x021b083c
-#define MMDC_P0_MPDGCTRL1	0x021b0840
-#define MMDC_P0_MPRDDLCTL	0x021b0848
-#define MMDC_P0_MPWRDLCTL	0x021b0850
-#define MMDC_P0_MPMUR0		0x021b08b8
-
-#define MMDC_P1_MDCTL		0x021b4000
-#define MMDC_P1_MDPDC		0x021b4004
-#define MMDC_P1_MDOTC		0x021b4008
-#define MMDC_P1_MDCFG0		0x021b400c
-#define MMDC_P1_MDCFG1		0x021b4010
-#define MMDC_P1_MDCFG2		0x021b4014
-#define MMDC_P1_MDMISC		0x021b4018
-#define MMDC_P1_MDSCR		0x021b401c
-#define MMDC_P1_MDREF		0x021b4020
-#define MMDC_P1_MDRWD		0x021b402c
-#define MMDC_P1_MDOR		0x021b4030
-#define MMDC_P1_MDASP		0x021b4040
-#define MMDC_P1_MAPSR		0x021b4404
-#define MMDC_P1_MPZQHWCTRL	0x021b4800
-#define MMDC_P1_MPWLDECTRL0	0x021b480c
-#define MMDC_P1_MPWLDECTRL1	0x021b4810
-#define MMDC_P1_MPODTCTRL	0x021b4818
-#define MMDC_P1_MPRDDQBY0DL	0x021b481c
-#define MMDC_P1_MPRDDQBY1DL	0x021b4820
-#define MMDC_P1_MPRDDQBY2DL	0x021b4824
-#define MMDC_P1_MPRDDQBY3DL	0x021b4828
-#define MMDC_P1_MPDGCTRL0	0x021b483c
-#define MMDC_P1_MPDGCTRL1	0x021b4840
-#define MMDC_P1_MPRDDLCTL	0x021b4848
-#define MMDC_P1_MPWRDLCTL	0x021b4850
-#define MMDC_P1_MPMUR0		0x021b48b8
-
-#define CCM_CCGR0		0x020C4068
-#define CCM_CCGR1		0x020C406c
-#define CCM_CCGR2		0x020C4070
-#define CCM_CCGR3		0x020C4074
-#define CCM_CCGR4		0x020C4078
-#define CCM_CCGR5		0x020C407c
-#define CCM_CCGR6		0x020C4080
+#define IOM_DRAM_DQM0		MA(0x5ac, 0x470, 0x0)
+#define IOM_DRAM_DQM1		MA(0x5b4, 0x474, 0x0)
+#define IOM_DRAM_DQM2		MA(0x528, 0x478, 0x0)
+#define IOM_DRAM_DQM3		MA(0x520, 0x47c, 0x0)
+#define IOM_DRAM_DQM4		MA(0x514, 0x480, 0x0)
+#define IOM_DRAM_DQM5		MA(0x510, 0x484, 0x0)
+#define IOM_DRAM_DQM6		MA(0x5bc, 0x488, 0x0)
+#define IOM_DRAM_DQM7		MA(0x5c4, 0x48c, 0x0)
+
+#define IOM_DRAM_CAS		MA(0x56c, 0x464, 0x0)
+#define IOM_DRAM_RAS		MA(0x578, 0x490, 0x0)
+#define IOM_DRAM_RESET		MA(0x57c, 0x494, 0x0)
+#define IOM_DRAM_SDCLK_0	MA(0x588, 0x4ac, 0x0)
+#define IOM_DRAM_SDCLK_1	MA(0x594, 0x4b0, 0x0)
+#define IOM_DRAM_SDBA2		MA(0x58c, 0x4a0, 0x0)
+#define IOM_DRAM_SDCKE0		MA(0x590, 0x4a4, 0x0)
+#define IOM_DRAM_SDCKE1		MA(0x598, 0x4a8, 0x0)
+#define IOM_DRAM_SDODT0		MA(0x59c, 0x4b4, 0x0)
+#define IOM_DRAM_SDODT1		MA(0x5a0, 0x4b8, 0x0)
+
+#define IOM_DRAM_SDQS0		MA(0x5a8, 0x4bc, 0x0)
+#define IOM_DRAM_SDQS1		MA(0x5b0, 0x4c0, 0x0)
+#define IOM_DRAM_SDQS2		MA(0x524, 0x4c4, 0x0)
+#define IOM_DRAM_SDQS3		MA(0x51c, 0x4c8, 0x0)
+#define IOM_DRAM_SDQS4		MA(0x518, 0x4cc, 0x0)
+#define IOM_DRAM_SDQS5		MA(0x50c, 0x4d0, 0x0)
+#define IOM_DRAM_SDQS6		MA(0x5b8, 0x4d4, 0x0)
+#define IOM_DRAM_SDQS7		MA(0x5c0, 0x4d8, 0x0)
+
+#define IOM_GRP_B0DS		MA(0x784, 0x764, 0x0)
+#define IOM_GRP_B1DS		MA(0x788, 0x770, 0x0)
+#define IOM_GRP_B2DS		MA(0x794, 0x778, 0x0)
+#define IOM_GRP_B3DS		MA(0x79c, 0x77c, 0x0)
+#define IOM_GRP_B4DS		MA(0x7a0, 0x780, 0x0)
+#define IOM_GRP_B5DS		MA(0x7a4, 0x784, 0x0)
+#define IOM_GRP_B6DS		MA(0x7a8, 0x78c, 0x0)
+#define IOM_GRP_B7DS		MA(0x748, 0x748, 0x0)
+#define IOM_GRP_ADDDS		MA(0x74c, 0x74c, 0x0)
+#define IOM_DDRMODE_CTL		MA(0x750, 0x750, 0x0)
+#define IOM_GRP_DDRPKE		MA(0x758, 0x754, 0x0)
+#define IOM_GRP_DDRMODE		MA(0x774, 0x760, 0x0)
+#define IOM_GRP_CTLDS		MA(0x78c, 0x76c, 0x0)
+#define IOM_GRP_DDR_TYPE	MA(0x798, 0x774, 0x0)
+
+#define MMDC_MDCTL		0x000
+#define MMDC_MDPDC		0x004
+#define MMDC_MDOTC		0x008
+#define MMDC_MDCFG0		0x00c
+#define MMDC_MDCFG1		0x010
+#define MMDC_MDCFG2		0x014
+#define MMDC_MDMISC		0x018
+#define MMDC_MDSCR		0x01c
+#define MMDC_MDREF		0x020
+#define MMDC_MDRWD		0x02c
+#define MMDC_MDOR		0x030
+#define MMDC_MDASP		0x040
+#define MMDC_MAPSR		0x404
+#define MMDC_MPZQHWCTRL		0x800
+#define MMDC_MPWLDECTRL0	0x80c
+#define MMDC_MPWLDECTRL1	0x810
+#define MMDC_MPODTCTRL		0x818
+#define MMDC_MPRDDQBY0DL	0x81c
+#define MMDC_MPRDDQBY1DL	0x820
+#define MMDC_MPRDDQBY2DL	0x824
+#define MMDC_MPRDDQBY3DL	0x828
+#define MMDC_MPDGCTRL0		0x83c
+#define MMDC_MPDGCTRL1		0x840
+#define MMDC_MPRDDLCTL		0x848
+#define MMDC_MPWRDLCTL		0x850
+#define MMDC_MPMUR0		0x8b8
+
+#define CCM_CCGR0		(CCM_BASE + 0x068)
+#define CCM_CCGR1		(CCM_BASE + 0x06c)
+#define CCM_CCGR2		(CCM_BASE + 0x070)
+#define CCM_CCGR3		(CCM_BASE + 0x074)
+#define CCM_CCGR4		(CCM_BASE + 0x078)
+#define CCM_CCGR5		(CCM_BASE + 0x07c)
+#define CCM_CCGR6		(CCM_BASE + 0x080)
 
 
 #define WRITE_ENTRY1(addr, q)		DATA 4, addr, q
 #ifdef CONFIG_MX6Q
-#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6q
+#define MA(mx6q, mx6dl_solo, mx6sololite)	(IOMUXC_BASE + mx6q)
 #define WRITE_ENTRY2(addr, q, dl)		WRITE_ENTRY1(addr, q)
 #define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, q)
 #define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, q)
@@ -131,20 +108,20 @@ 
 
 #define WRITE_ENTRY2(addr, q, dl)		WRITE_ENTRY1(addr, dl)
 #ifdef CONFIG_MX6DL
-#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6dl_solo
+#define MA(mx6q, mx6dl_solo, mx6sololite)	(IOMUXC_BASE + mx6dl_solo)
 #define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, dl)
 #define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, dl)
 #else
 
 #define WRITE_ENTRY3(addr, q, dl, solo)		WRITE_ENTRY1(addr, solo)
 #ifdef CONFIG_MX6S
-#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6dl_solo
+#define MA(mx6q, mx6dl_solo, mx6sololite)	(IOMUXC_BASE + mx6dl_solo)
 #define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, solo)
 #else
 
 #define WRITE_ENTRY4(addr, q, dl, solo, sl)	WRITE_ENTRY1(addr, sl)
 #ifdef CONFIG_MX6SL
-#define MA(mx6q, mx6dl_solo, mx6sololite)	mx6sololite
+#define MA(mx6q, mx6dl_solo, mx6sololite)	(IOMUXC_BASE + mx6sololite)
 #else
 
 #error "Please select cpu"
diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index f45f93e..5de0f30 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -111,24 +111,24 @@  WRITE_ENTRY1(IOM_GRP_CTLDS, 0x00000030)
 WRITE_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000)
 
 /* Read data DQ Byte0-3 delay */
-WRITE_ENTRY1(MMDC_P0_MPRDDQBY0DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P0_MPRDDQBY1DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P0_MPRDDQBY2DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P0_MPRDDQBY3DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P1_MPRDDQBY0DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P1_MPRDDQBY1DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P1_MPRDDQBY2DL, 0x33333333)
-WRITE_ENTRY1(MMDC_P1_MPRDDQBY3DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPRDDQBY3DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY0DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY1DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY2DL, 0x33333333)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPRDDQBY3DL, 0x33333333)
 
 /*
  * MDMISC, mirroring, interleaved (row/bank/col)
  */
-WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDMISC, 0x00081740)
 
 /*
  * MDSCR, con_req
  */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008000)
 
 /*
  * MDCFG0,
@@ -139,7 +139,7 @@  WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000)
  *	tRFC=0x6a clocks, tXS=0x6e clocks, tXP=3 clocks, tXPDLL=10 clocks
  *	 tFAW=19 clocks, cas=6 cycles
  */
-WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDCFG0, 0x555A7975, 0x696D5323)
 
 /*
  * MDCFG1,
@@ -148,14 +148,14 @@  WRITE_ENTRY2(MMDC_P0_MDCFG0, 0x555A7975, 0x696D5323)
  * MX6DL/SOLO:
  *	tRDC=6, tRP=6, tRC=20, tRAS=15, tRPA=tRP+1, tWR=7, tMRD=4, tCWL=5
  */
-WRITE_ENTRY2(MMDC_P0_MDCFG1, 0xFF538E64, 0xB66E8C63)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDCFG1, 0xFF538E64, 0xB66E8C63)
 
 /*
  * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4
  */
-WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB)
-WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2)
-WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDCFG2, 0x01FF00DB)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDRWD, 0x000026D2)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDOR, 0x005B0E21)
 
 /*
  * MMDC_MDOTC,
@@ -164,7 +164,7 @@  WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21)
  * MX6DL/SOLO:
  *	tAOFPD=1 cycles, tAONPD=1, tANPD=4, tAXPD=4, tODTLon=4, tODT_idle_off=4
  */
-WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDOTC, 0x09444040, 0x00333030)
 
 /*
  * MDPDC - [17:16](2) => CKE pulse width = 3 cycles.
@@ -173,7 +173,7 @@  WRITE_ENTRY2(MMDC_P0_MDOTC, 0x09444040, 0x00333030)
  * MX6Q:       [2:0](6) => CKSRE = 6 cycles, [5:3](6) => CKSRX = 6 cycles
  * MX6DL/SOLO: [2:0](5) => CKSRE = 5 cycles, [5:3](5) => CKSRX = 5 cycles
  */
-WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDPDC, 0x00025576, 0x0002556D)
 
 /*
  * MX6Q/DL - 64 bit wide ddr
@@ -186,68 +186,68 @@  WRITE_ENTRY2(MMDC_P0_MDPDC, 0x00025576, 0x0002556D)
  *	1<<3 + 1<<4 - 1 = 8 + 0x10 -1 = 0x17
  */
 /* MDASP, CS0_END */
-WRITE_ENTRY3(MMDC_P0_MDASP, 0x00000027, 0x00000027, 0x00000017)
+WRITE_ENTRY3(MMDC_P0 + MMDC_MDASP, 0x00000027, 0x00000027, 0x00000017)
 /*
  * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8
  * MX6Q/DL: width=64bit row+col+bank+width=14+10+3+3=30 = 1G
  * MX6SOLO: width=32bit row+col+bank+width=14+10+3+2=29 = 512M
  */
-WRITE_ENTRY3(MMDC_P0_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
+WRITE_ENTRY3(MMDC_P0 + MMDC_MDCTL, 0x831A0000, 0x831A0000, 0x83190000)
 
 /*
  * LOAD MR2: MDSCR, con_req,  CS0, A10 set - RZQ/2
  * MX6Q:    A3 set(CAS Write=6)
  * MX6DL/SOLO: (CAS Write=5)
  */
-WRITE_ENTRY2(MMDC_P0_MDSCR, 0x04088032, 0x04008032)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x04088032, 0x04008032)
 /* LOAD MR3, CS0 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00008033)
 
 /*
  * LOAD MR1, CS0
  * MX6Q: A6 set: Rtt=RZQ/2, A1 set: ODI=RZQ/7
  * MX6DL/SOLO: A2 set: Rtt=RZQ/4, ODI=RZQ/6
  */
-WRITE_ENTRY2(MMDC_P0_MDSCR, 0x00428031, 0x00048031)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x00428031, 0x00048031)
 
 /* LOAD MR0, CS0 A8 set: DLL Reset
  * MX6Q: A6 set: CAS=8 A11 set: WR=8
  * MX6DL/SOLO: A4 set: CAS=5, A9,A10 set: WR=7
  */
-WRITE_ENTRY2(MMDC_P0_MDSCR, 0x09408030, 0x07208030)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MDSCR, 0x09408030, 0x07208030)
 
 /* ZQ calibrate, CS0 */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040)
-WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1390003)
-WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1390003)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x04008040)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPZQHWCTRL, 0xA1390003)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPZQHWCTRL, 0xA1390003)
 
 /* MDREF,  32KHz refresh, 4 refeshes each */
-WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800)
-WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227)
-WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDREF, 0x00005800)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPODTCTRL, 0x00022227)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPODTCTRL, 0x00022227)
 
 /* MPDGCTRL0/1 DQS GATE*/
-WRITE_ENTRY2(MMDC_P0_MPDGCTRL0, 0x434B0350, 0x42350231)
-WRITE_ENTRY2(MMDC_P0_MPDGCTRL1, 0x034C0359, 0x021A0218)
-WRITE_ENTRY2(MMDC_P1_MPDGCTRL0, 0x434B0350, 0x42350231)
-WRITE_ENTRY2(MMDC_P1_MPDGCTRL1, 0x03650348, 0x021A0218)
-WRITE_ENTRY2(MMDC_P0_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
-WRITE_ENTRY2(MMDC_P1_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
-WRITE_ENTRY2(MMDC_P0_MPWRDLCTL, 0x35373933, 0x3F3F3035)
-WRITE_ENTRY2(MMDC_P1_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
-WRITE_ENTRY2(MMDC_P0_MPWLDECTRL0, 0x001F001F, 0x0040003C)
-WRITE_ENTRY2(MMDC_P0_MPWLDECTRL1, 0x001F001F, 0x0032003E)
-WRITE_ENTRY2(MMDC_P1_MPWLDECTRL0, 0x00440044, 0x0040003C)
-WRITE_ENTRY2(MMDC_P1_MPWLDECTRL1, 0x00440044, 0x0032003E)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPDGCTRL1, 0x034C0359, 0x021A0218)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPDGCTRL0, 0x434B0350, 0x42350231)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPDGCTRL1, 0x03650348, 0x021A0218)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPRDDLCTL, 0x4436383B, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPRDDLCTL, 0x39393341, 0x4B4B4E49)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWRDLCTL, 0x35373933, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWRDLCTL, 0x48254A36, 0x3F3F3035)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWLDECTRL0, 0x001F001F, 0x0040003C)
+WRITE_ENTRY2(MMDC_P0 + MMDC_MPWLDECTRL1, 0x001F001F, 0x0032003E)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWLDECTRL0, 0x00440044, 0x0040003C)
+WRITE_ENTRY2(MMDC_P1 + MMDC_MPWLDECTRL1, 0x00440044, 0x0032003E)
 
 /* MPMUR0 - Complete calibration by forced measurement */
-WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800)
-WRITE_ENTRY1(MMDC_P1_MPMUR0, 0x00000800)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MPMUR0, 0x00000800)
+WRITE_ENTRY1(MMDC_P1 + MMDC_MPMUR0, 0x00000800)
 
 /* MDSCR, enable ddr */
-WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00000000)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MDSCR, 0x00000000)
 /* MAPSR, 1024 cycles idle before self-refresh */
-WRITE_ENTRY1(MMDC_P0_MAPSR, 0x00011006)
+WRITE_ENTRY1(MMDC_P0 + MMDC_MAPSR, 0x00011006)
 
 /* set the default clock gate to save power */
 WRITE_ENTRY1(CCM_CCGR0, 0x00C03F3F)