From patchwork Thu Oct 4 01:47:21 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Troy Kisky X-Patchwork-Id: 188996 X-Patchwork-Delegate: sbabic@denx.de Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 955132C0333 for ; Thu, 4 Oct 2012 11:50:15 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 0583128339; Thu, 4 Oct 2012 03:49:31 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id 2PCQg6PW-NL1; Thu, 4 Oct 2012 03:49:30 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id ED20F281DA; Thu, 4 Oct 2012 03:48:05 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 3CBA428234 for ; Thu, 4 Oct 2012 03:47:48 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZVbdaGl4omFG for ; Thu, 4 Oct 2012 03:47:47 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-da0-f44.google.com (mail-da0-f44.google.com [209.85.210.44]) by theia.denx.de (Postfix) with ESMTPS id 0262228220 for ; Thu, 4 Oct 2012 03:47:37 +0200 (CEST) Received: by danh15 with SMTP id h15so2684566dan.3 for ; Wed, 03 Oct 2012 18:47:35 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=7otZh7Z04MASH42Tko53wcsauPZ32RqRflF+Y3QGpKs=; b=eeuGM24mx8ry4rtH6z/A8WDguC9+BcHLiR4qvUwSxxt3e0g3kUVEXUsKRqJA8xSELm 87MsrGwywZ48N7d/kAA/7iE88Fl6y5NAjgVKkRj2D8dnlAJm1ceIFawCaEWYIhZkpSrp uzK4/TN9S80aouhpZ04ipO+FwyhADZB/EJgpSuTp8bjEfbv26v30s9ZIiafnYhdHPzuU qkNThd98x4wLgN8ShgGKy4XyKiNsvJKx9cIb1riL2nqKe/pYgnbi3ci90AW4zWa/Aa0f pvExf5dGBwIQeOgixoBt84RiQaaviO/vkf5bhglT1VycCpRRd/i30adFjRuq0LTE2dq/ lhNQ== Received: by 10.66.77.168 with SMTP id t8mr9389340paw.28.1349315255745; Wed, 03 Oct 2012 18:47:35 -0700 (PDT) Received: from officeserver-2 ([70.96.116.236]) by mx.google.com with ESMTPS id h10sm3352134pav.28.2012.10.03.18.47.33 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 03 Oct 2012 18:47:35 -0700 (PDT) Received: from tkisky by officeserver-2 with local (Exim 4.76) (envelope-from ) id 1TJaXd-0005X0-Jl; Wed, 03 Oct 2012 18:47:57 -0700 From: Troy Kisky To: sbabic@denx.de Date: Wed, 3 Oct 2012 18:47:21 -0700 Message-Id: <1349315254-21151-20-git-send-email-troy.kisky@boundarydevices.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1349315254-21151-1-git-send-email-troy.kisky@boundarydevices.com> References: <1348281558-19520-1-git-send-email-troy.kisky@boundarydevices.com> <1349315254-21151-1-git-send-email-troy.kisky@boundarydevices.com> X-Gm-Message-State: ALoCoQnvr7p0mmQkrUgTsszDKdnKM4Jjd1vB/2NBY24PG9W/YcG1VwUEy2QU4jjPAgRRe+q2QttT Cc: u-boot@lists.denx.de Subject: [U-Boot] [PATCH V3 19/32] mx6q_4x_mt41j128.cfg: add comments X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de Signed-off-by: Troy Kisky --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 55 ++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 84823f8..b859e2f 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -53,7 +53,6 @@ WRITE_ENTRY1(IOM_DRAM_SDQS0, 0x00000030) WRITE_ENTRY1(IOM_DRAM_SDQS1, 0x00000030) WRITE_ENTRY1(IOM_DRAM_SDQS2, 0x00000030) WRITE_ENTRY1(IOM_DRAM_SDQS3, 0x00000030) - WRITE_ENTRY1(IOM_DRAM_SDQS4, 0x00000030) WRITE_ENTRY1(IOM_DRAM_SDQS5, 0x00000030) WRITE_ENTRY1(IOM_DRAM_SDQS6, 0x00000030) @@ -63,7 +62,6 @@ WRITE_ENTRY1(IOM_DRAM_DQM0, 0x00020030) WRITE_ENTRY1(IOM_DRAM_DQM1, 0x00020030) WRITE_ENTRY1(IOM_DRAM_DQM2, 0x00020030) WRITE_ENTRY1(IOM_DRAM_DQM3, 0x00020030) - WRITE_ENTRY1(IOM_DRAM_DQM4, 0x00020030) WRITE_ENTRY1(IOM_DRAM_DQM5, 0x00020030) WRITE_ENTRY1(IOM_DRAM_DQM6, 0x00020030) @@ -81,65 +79,105 @@ WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000) WRITE_ENTRY1(IOM_DRAM_SDODT0, 0x00003030) WRITE_ENTRY1(IOM_DRAM_SDODT1, 0x00003030) + WRITE_ENTRY1(IOM_GRP_B0DS, 0x00000030) WRITE_ENTRY1(IOM_GRP_B1DS, 0x00000030) - WRITE_ENTRY1(IOM_GRP_B2DS, 0x00000030) WRITE_ENTRY1(IOM_GRP_B3DS, 0x00000030) WRITE_ENTRY1(IOM_GRP_B4DS, 0x00000030) WRITE_ENTRY1(IOM_GRP_B5DS, 0x00000030) - WRITE_ENTRY1(IOM_GRP_B6DS, 0x00000030) WRITE_ENTRY1(IOM_GRP_B7DS, 0x00000030) + WRITE_ENTRY1(IOM_GRP_ADDDS, 0x00000030) +/* (differential input) */ WRITE_ENTRY1(IOM_DDRMODE_CTL, 0x00020000) - +/* disable ddr pullups */ WRITE_ENTRY1(IOM_GRP_DDRPKE, 0x00000000) +/* (differential input) */ WRITE_ENTRY1(IOM_GRP_DDRMODE, 0x00020000) +/* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */ WRITE_ENTRY1(IOM_GRP_CTLDS, 0x00000030) WRITE_ENTRY1(IOM_GRP_DDR_TYPE, 0x000C0000) +/* Read data DQ Byte0-3 delay */ WRITE_ENTRY1(MMDC_P0_MPRDDQBY0DL, 0x33333333) WRITE_ENTRY1(MMDC_P0_MPRDDQBY1DL, 0x33333333) WRITE_ENTRY1(MMDC_P0_MPRDDQBY2DL, 0x33333333) WRITE_ENTRY1(MMDC_P0_MPRDDQBY3DL, 0x33333333) - WRITE_ENTRY1(MMDC_P1_MPRDDQBY0DL, 0x33333333) WRITE_ENTRY1(MMDC_P1_MPRDDQBY1DL, 0x33333333) WRITE_ENTRY1(MMDC_P1_MPRDDQBY2DL, 0x33333333) WRITE_ENTRY1(MMDC_P1_MPRDDQBY3DL, 0x33333333) +/* + * MDMISC, mirroring, interleaved (row/bank/col) + */ WRITE_ENTRY1(MMDC_P0_MDMISC, 0x00081740) +/* + * MDSCR, con_req + */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008000) +/* + * MDCFG0, tRFC=0x56 clocks, tXS=0x5b clocks + * tXP=4 clocks, tXPDLL=13 clocks + * tFAW=24 clocks, cas=8 cycles + */ WRITE_ENTRY1(MMDC_P0_MDCFG0, 0x555A7975) +/* + * MDCFG1, tRDC=8, tRP=8, tRC=27,tRAS=20,tRPA=tRP+1,tWR=8 + * tMRD=4, tCWL=6 + */ WRITE_ENTRY1(MMDC_P0_MDCFG1, 0xFF538E64) +/* + * MDCFG2,tDLLK=512,tRTP=4,tWTR=4,tRRD=4 + */ WRITE_ENTRY1(MMDC_P0_MDCFG2, 0x01FF00DB) WRITE_ENTRY1(MMDC_P0_MDRWD, 0x000026D2) WRITE_ENTRY1(MMDC_P0_MDOR, 0x005B0E21) WRITE_ENTRY1(MMDC_P0_MDOTC, 0x09444040) WRITE_ENTRY1(MMDC_P0_MDPDC, 0x00025576) + +/* + * Mx6Q - 64 bit wide ddr + * last address is (1<<28 (base) + 1<<30 - 1) / (1<<25) = + * 1<<3 + 1<<5 - 1 = 8 + 0x20 -1 = 0x27 + */ +/* MDASP, CS0_END */ WRITE_ENTRY1(MMDC_P0_MDASP, 0x00000027) +/* + * MDCTL, CS0 enable, CS1 disabled, row=14, col=10, burst=8, width=64/32bit + * mx6q : row+col+bank+width=14+10+3+3=30 = 1G + */ WRITE_ENTRY1(MMDC_P0_MDCTL, 0x831A0000) +/* MDSCR, con_req, LOAD MR2, CS0, A3,A10 set (CAS Write=6), RZQ/2 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04088032) WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0408803A) +/* LOAD MR3, CS0 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00008033) WRITE_ENTRY1(MMDC_P0_MDSCR, 0x0000803B) +/* LOAD MR1, CS0, A1,A6 set Rtt=RZQ/2, ODI=RZQ/7 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428031) WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00428039) +/* LOAD MR0, CS0, A6,A8,A11 set CAS=8, WR=8, DLL reset */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030) WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408038) +/* ZQ calibrate, CS0 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040) WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008048) WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003) WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003) + +/* MDREF, 32KHz refresh, 4 refeshes each */ WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800) WRITE_ENTRY1(MMDC_P0_MPODTCTRL, 0x00022227) WRITE_ENTRY1(MMDC_P1_MPODTCTRL, 0x00022227) +/* MPDGCTRL0/1 DQS GATE*/ WRITE_ENTRY1(MMDC_P0_MPDGCTRL0, 0x434B0350) WRITE_ENTRY1(MMDC_P0_MPDGCTRL1, 0x034C0359) WRITE_ENTRY1(MMDC_P1_MPDGCTRL0, 0x434B0350) @@ -148,17 +186,18 @@ WRITE_ENTRY1(MMDC_P0_MPRDDLCTL, 0x4436383B) WRITE_ENTRY1(MMDC_P1_MPRDDLCTL, 0x39393341) WRITE_ENTRY1(MMDC_P0_MPWRDLCTL, 0x35373933) WRITE_ENTRY1(MMDC_P1_MPWRDLCTL, 0x48254A36) - WRITE_ENTRY1(MMDC_P0_MPWLDECTRL0, 0x001F001F) WRITE_ENTRY1(MMDC_P0_MPWLDECTRL1, 0x001F001F) - WRITE_ENTRY1(MMDC_P1_MPWLDECTRL0, 0x00440044) WRITE_ENTRY1(MMDC_P1_MPWLDECTRL1, 0x00440044) +/* MPMUR0 - Complete calibration by forced measurement */ WRITE_ENTRY1(MMDC_P0_MPMUR0, 0x00000800) WRITE_ENTRY1(MMDC_P1_MPMUR0, 0x00000800) +/* MDSCR, enable ddr */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x00000000) +/* MAPSR, 1024 cycles idle before self-refresh */ WRITE_ENTRY1(MMDC_P0_MAPSR, 0x00011006) /* set the default clock gate to save power */