Patchwork [U-Boot,V3,20/32] mx6q_4x_mt41j128.cfg: use ddr3 mode for reset

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Submitter Troy Kisky
Date Oct. 4, 2012, 1:47 a.m.
Message ID <1349315254-21151-21-git-send-email-troy.kisky@boundarydevices.com>
Download mbox | patch
Permalink /patch/188992/
State Changes Requested
Delegated to: Stefano Babic
Headers show

Comments

Troy Kisky - Oct. 4, 2012, 1:47 a.m.
Bits 19-18 of IOMUXC_IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET
should be 3 for DDR3 mode. The current value of 0 is
reserved in TRM.

Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
---
 board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Patch

diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
index b859e2f..9c622c8 100644
--- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
+++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg
@@ -72,7 +72,7 @@  WRITE_ENTRY1(IOM_DRAM_RAS, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_SDCLK_0, 0x00020030)
 WRITE_ENTRY1(IOM_DRAM_SDCLK_1, 0x00020030)
 
-WRITE_ENTRY1(IOM_DRAM_RESET, 0x00020030)
+WRITE_ENTRY1(IOM_DRAM_RESET, 0x000e0030)
 WRITE_ENTRY1(IOM_DRAM_SDCKE0, 0x00003000)
 WRITE_ENTRY1(IOM_DRAM_SDCKE1, 0x00003000)
 WRITE_ENTRY1(IOM_DRAM_SDBA2, 0x00000000)