From patchwork Thu Oct 4 01:47:24 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot,V3,22/32] mx6q_4x_mt41j128.cfg: force ZQ calibration From: Troy Kisky X-Patchwork-Id: 188984 Message-Id: <1349315254-21151-23-git-send-email-troy.kisky@boundarydevices.com> To: sbabic@denx.de Cc: u-boot@lists.denx.de Date: Wed, 3 Oct 2012 18:47:24 -0700 Signed-off-by: Troy Kisky --- board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg index 2d03ff7..9e20db0 100644 --- a/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg +++ b/board/freescale/imx/ddr/mx6q_4x_mt41j128.cfg @@ -164,8 +164,8 @@ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x09408030) /* ZQ calibrate, CS0 */ WRITE_ENTRY1(MMDC_P0_MDSCR, 0x04008040) -WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1380003) -WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1380003) +WRITE_ENTRY1(MMDC_P0_MPZQHWCTRL, 0xA1390003) +WRITE_ENTRY1(MMDC_P1_MPZQHWCTRL, 0xA1390003) /* MDREF, 32KHz refresh, 4 refeshes each */ WRITE_ENTRY1(MMDC_P0_MDREF, 0x00005800)