From patchwork Thu Oct 4 00:39:27 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Glass X-Patchwork-Id: 188974 X-Patchwork-Delegate: graeme.russ@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 875F42C007F for ; Thu, 4 Oct 2012 10:40:41 +1000 (EST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id AD6F328244; Thu, 4 Oct 2012 02:40:33 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id tP0gxY5Imd8K; Thu, 4 Oct 2012 02:40:33 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id BFE612821E; Thu, 4 Oct 2012 02:40:12 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id D2A85281F5 for ; Thu, 4 Oct 2012 02:40:06 +0200 (CEST) X-Virus-Scanned: Debian amavisd-new at theia.denx.de Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id HqpqjMQCtDh0 for ; Thu, 4 Oct 2012 02:40:06 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from mail-wi0-f202.google.com (mail-wi0-f202.google.com [209.85.212.202]) by theia.denx.de (Postfix) with ESMTPS id 2FD2B281FF for ; Thu, 4 Oct 2012 02:39:59 +0200 (CEST) Received: by wibhr7 with SMTP id hr7so163520wib.3 for ; Wed, 03 Oct 2012 17:39:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :x-gm-message-state; bh=o/RjZai0meOy6Lwesd5DTAFlM3cur4AhcYnrlumEGKE=; b=ak05BzO7rtGUgtVAl6m8UNqbToAXqBT7KCtll7a+0dcH76EiCo8ZxY02FkzJL+jYhT IdtiAvlUBg4GSyFi8VkTawnTzVOjCCAQZPqjO0bEx0mr+uok4yC2RqQmOYt8HZe+yKPd OAu48pC33nSu/1AUqTWcCOd+qi7D8bk/bNCnjjGp3VNcX+c9ptMim6pzB1FSUu28DM+V ljqjZzqgkIjN/qGakGDYHwSlHNOy+ra6wtBXjljRSkvm4IDrv4Q/OHas4+VIV8h1T++U jdJl7iaxFqbhOS7Ew1S4eQwZ9t8Xna5fLMRaPzHGVNv35rquqfaB7hM1jz3QaBu85YyE wYVQ== Received: by 10.216.239.205 with SMTP id c55mr217163wer.12.1349311198800; Wed, 03 Oct 2012 17:39:58 -0700 (PDT) Received: from hpza9.eem.corp.google.com ([74.125.121.33]) by gmr-mx.google.com with ESMTPS id fb20si1550316wid.3.2012.10.03.17.39.58 (version=TLSv1/SSLv3 cipher=AES128-SHA); Wed, 03 Oct 2012 17:39:58 -0700 (PDT) Received: from kaka.mtv.corp.google.com (kaka.mtv.corp.google.com [172.22.73.79]) by hpza9.eem.corp.google.com (Postfix) with ESMTP id 657F85C0060; Wed, 3 Oct 2012 17:39:58 -0700 (PDT) Received: by kaka.mtv.corp.google.com (Postfix, from userid 121222) id A909E160557; Wed, 3 Oct 2012 17:39:57 -0700 (PDT) From: Simon Glass To: U-Boot Mailing List Date: Wed, 3 Oct 2012 17:39:27 -0700 Message-Id: <1349311168-3524-9-git-send-email-sjg@chromium.org> X-Mailer: git-send-email 1.7.7.3 In-Reply-To: <1349311168-3524-1-git-send-email-sjg@chromium.org> References: <1349311168-3524-1-git-send-email-sjg@chromium.org> X-Gm-Message-State: ALoCoQmO2AI8BqYhYfRs1GbXcz7fy3QKL5Aa6LW5ntAfHEJIKlMQaBPL2DgsfFZQgFbPPzxifG+xi2OiOYZ/4ipkjBwcqhgWddLykA1A84hFSFtwkxXiD2UX107OnACUvrSgjvb4CwZjwbetj9U04aAhaAAjTz8UVdrFdeLChsxMUcqmdfYh8WVJXbzyCekQlTxG8501YQs2 Cc: Stefan Reinauer , Vincent Palatin , Vadim Bendebury Subject: [U-Boot] [PATCH 8/9] x86: coreboot: Implement recursively scanning PCI busses X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.11 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: u-boot-bounces@lists.denx.de Errors-To: u-boot-bounces@lists.denx.de From: Gabe Black A hook is installed to configure PCI bus bridges as they encountered by u-boot. The hook extracts the secondary bus number from the bridge's config space and then recursively scans that bus. On Coreboot, the PCI bus address space has identity mapping with the physical address space, so declare it as such to ensure that the "pci_map_bar" function used by some PCI drivers is behaving properly. This fixes the EHCI PCI driver initialization on Stumpy. This was tested as follows: Ran the PCI command on Alex, saw devices on bus 0, the OXPCIe 952 on bus 1, and empty busses 2 through 5. This matches the bridges reported on bus 0 and the PCI configuration output from coreboot. Signed-off-by: Gabe Black Signed-off-by: Vincent Palatin Signed-off-by: Stefan Reinauer Signed-off-by: Simon Glass --- arch/x86/cpu/coreboot/pci.c | 26 +++++++++++++++++++++++--- 1 files changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c index 0ddc975..8f94167 100644 --- a/arch/x86/cpu/coreboot/pci.c +++ b/arch/x86/cpu/coreboot/pci.c @@ -31,15 +31,35 @@ static struct pci_controller coreboot_hose; +static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev, + struct pci_config_table *table) +{ + u8 secondary; + hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary); + hose->last_busno = max(hose->last_busno, secondary); + pci_hose_scan_bus(hose, secondary); +} + +static struct pci_config_table pci_coreboot_config_table[] = { + /* vendor, device, class, bus, dev, func */ + { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI, + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge }, + {} +}; + void pci_init_board(void) { + coreboot_hose.config_table = pci_coreboot_config_table; coreboot_hose.first_busno = 0; - coreboot_hose.last_busno = 0xff; - coreboot_hose.region_count = 0; + coreboot_hose.last_busno = 0; + + pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff, + PCI_REGION_MEM); + coreboot_hose.region_count = 1; pci_setup_type1(&coreboot_hose); pci_register_hose(&coreboot_hose); - coreboot_hose.last_busno = pci_hose_scan(&coreboot_hose); + pci_hose_scan(&coreboot_hose); }