Patchwork [U-Boot,9/9] x86: coreboot: Enable LPC TPM and CONFIG_NO_RESET_CODE

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Submitter Simon Glass
Date Oct. 4, 2012, 12:39 a.m.
Message ID <1349311168-3524-10-git-send-email-sjg@chromium.org>
Download mbox | patch
Permalink /patch/188973/
State Superseded, archived
Delegated to: Graeme Russ
Headers show

Comments

Simon Glass - Oct. 4, 2012, 12:39 a.m.
Coreboot boards have an LPC TPM connected, so enable this. We also need
to skip the reset code.

Signed-off-by: Simon Glass <sjg@chromium.org>
---
 include/configs/coreboot.h |    6 +++++-
 1 files changed, 5 insertions(+), 1 deletions(-)
Gabe Black - Oct. 4, 2012, 1:13 a.m.
Acked-by: Gabe Black <gabeblack@chromium.org>

Patch

diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h
index 2c65d74..75db176 100644
--- a/include/configs/coreboot.h
+++ b/include/configs/coreboot.h
@@ -37,7 +37,7 @@ 
 #define CONFIG_SYS_COREBOOT
 #undef CONFIG_SHOW_BOOT_PROGRESS
 #define CONFIG_LAST_STAGE_INIT
-
+#define CONFIG_NO_RESET_CODE
 
 /*-----------------------------------------------------------------------
  * Watchdog Configuration
@@ -45,6 +45,10 @@ 
 #undef CONFIG_WATCHDOG
 #undef CONFIG_HW_WATCHDOG
 
+/* Generic TPM interfaced through LPC bus */
+#define CONFIG_GENERIC_LPC_TPM
+#define CONFIG_TPM_TIS_BASE_ADDRESS        0xfed40000
+
 /*-----------------------------------------------------------------------
  * Real Time Clock Configuration
  */