From patchwork Thu Oct 4 00:16:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peter A. G. Crosthwaite" X-Patchwork-Id: 188969 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 7E28D2C0333 for ; Thu, 4 Oct 2012 10:27:21 +1000 (EST) Received: from localhost ([::1]:39407 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJZ7u-0000bv-3u for incoming@patchwork.ozlabs.org; Wed, 03 Oct 2012 20:17:18 -0400 Received: from eggs.gnu.org ([208.118.235.92]:49064) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJZ7I-0007PI-Gi for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJZ7G-00051o-Lw for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:40 -0400 Received: from mail-pa0-f45.google.com ([209.85.220.45]:48566) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJZ7G-00050D-GE for qemu-devel@nongnu.org; Wed, 03 Oct 2012 20:16:38 -0400 Received: by mail-pa0-f45.google.com with SMTP id fb10so6962194pad.4 for ; Wed, 03 Oct 2012 17:16:38 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=from:to:cc:subject:date:message-id:x-mailer:in-reply-to:references :in-reply-to:references:x-gm-message-state; bh=uKQTLJ0VMkMbQQTyfK1/s1l5FfO542UKZkdpaQRTb84=; b=hX91syFG8ZUA2gzTwWMNDTGa20AK111ByQlcW8I0lMTNbYYiAmsGwso8WVsKoqkOW/ 9PdEQEazFPffo8z1eOeX3qyr0KnZxnwnLG/I0uSslPEKeLDNCtglaHMJSrgUsercHMsI 0TX0hOkb8/kZ/U3XRLnymFElHw8vQ4yb0SSBxgWJYj+r2Hus2f5qAPZqy2i+Ojtc47zH 7bFFwmrZ4B+Y/RDky7Y1E33bfkiMTV+SDrJ5GAHVkfbVsVW/fLM6/UfpR4vMmnwxtq2+ 31NsTvaojTgqD2kEQrsdFTKOeCI7B83O4NGEi+HuDax24ngiYprkD+g4o5Lbk3PIhn8b TOYw== Received: by 10.66.78.69 with SMTP id z5mr8946760paw.14.1349309798157; Wed, 03 Oct 2012 17:16:38 -0700 (PDT) Received: from localhost ([124.148.20.9]) by mx.google.com with ESMTPS id w4sm3235495pav.27.2012.10.03.17.16.35 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 03 Oct 2012 17:16:37 -0700 (PDT) From: Peter Crosthwaite To: qemu-devel@nongnu.org, peter.maydell@linaro.org, edgar.iglesias@gmail.com Date: Thu, 4 Oct 2012 10:16:14 +1000 Message-Id: X-Mailer: git-send-email 1.7.0.4 In-Reply-To: References: In-Reply-To: References: X-Gm-Message-State: ALoCoQl3Lma2WQKVuNBjguYY4CRp7agPg+VxoKJVA/+BijyAAuIsmF4R/Mmc+DpNHMjRdtvnvMy2 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.85.220.45 Cc: linnj@xilinx.com, "Peter A. G. Crosthwaite" , john.williams@petalogix.com Subject: [Qemu-devel] [PATCH v2 4/4] zynq_slcr: Implement CPU reset and halting X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org From: Peter A. G. Crosthwaite Implement the CPU reset and halt functions of the A9_CPU_RST_CTRL register (offset 0x244). Signed-off-by: Peter A. G. Crosthwaite --- hw/zynq_slcr.c | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/hw/zynq_slcr.c b/hw/zynq_slcr.c index 6eafad5..c1922fc 100644 --- a/hw/zynq_slcr.c +++ b/hw/zynq_slcr.c @@ -116,6 +116,9 @@ typedef enum { RESET_MAX } ResetValues; +#define A9_CPU_RST_CTRL_RST_SHIFT 0 +#define A9_CPU_RST_CTRL_CLKSTOP_SHIFT 4 + typedef struct { SysBusDevice busdev; MemoryRegion iomem; @@ -346,6 +349,7 @@ static void zynq_slcr_write(void *opaque, target_phys_addr_t offset, uint64_t val, unsigned size) { ZynqSLCRState *s = (ZynqSLCRState *)opaque; + int i; DB_PRINT("offset: %08x data: %08x\n", offset, (unsigned)val); @@ -400,6 +404,20 @@ static void zynq_slcr_write(void *opaque, target_phys_addr_t offset, goto bad_reg; } s->reset[(offset - 0x200) / 4] = val; + if (offset - 0x200 == A9_CPU * 4) { /* CPU Reset */ + for (i = 0; i < NUM_CPUS && s->cpus[i]; ++i) { + bool is_rst = val & (1 << (A9_CPU_RST_CTRL_RST_SHIFT + i)); + bool is_clkstop = val & + (1 << (A9_CPU_RST_CTRL_CLKSTOP_SHIFT + i)); + if (is_rst) { + CPU_GET_CLASS(CPU(s->cpus[i]))->reset(CPU(s->cpus[i])); + DB_PRINT("resetting cpu %d\n", i); + } + s->cpus[i]->env.halted = is_rst || is_clkstop; + DB_PRINT("%shalting cpu %d\n", s->cpus[i]->env.halted ? + "" : "un", i); + } + } break; case 0x300: s->apu_ctrl = val;