From patchwork Wed Oct 3 13:29:14 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Eduardo Habkost X-Patchwork-Id: 188783 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) (using TLSv1 with cipher AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id B98DA2C00BC for ; Thu, 4 Oct 2012 00:20:27 +1000 (EST) Received: from localhost ([::1]:40092 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJP0x-0006Qq-75 for incoming@patchwork.ozlabs.org; Wed, 03 Oct 2012 09:29:27 -0400 Received: from eggs.gnu.org ([208.118.235.92]:37159) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJP01-0004BN-2o for qemu-devel@nongnu.org; Wed, 03 Oct 2012 09:28:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1TJOzu-0006cJ-5R for qemu-devel@nongnu.org; Wed, 03 Oct 2012 09:28:28 -0400 Received: from mx1.redhat.com ([209.132.183.28]:64708) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1TJOzt-0006bv-TM for qemu-devel@nongnu.org; Wed, 03 Oct 2012 09:28:22 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id q93DSLtO028504 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Wed, 3 Oct 2012 09:28:21 -0400 Received: from blackpad.lan.raisama.net (vpn1-7-147.gru2.redhat.com [10.97.7.147]) by int-mx11.intmail.prod.int.phx2.redhat.com (8.14.4/8.14.4) with ESMTP id q93DSKFG025450; Wed, 3 Oct 2012 09:28:20 -0400 Received: by blackpad.lan.raisama.net (Postfix, from userid 500) id 6C8CB20360B; Wed, 3 Oct 2012 10:29:22 -0300 (BRT) From: Eduardo Habkost To: qemu-devel@nongnu.org Date: Wed, 3 Oct 2012 10:29:14 -0300 Message-Id: <1349270954-4657-19-git-send-email-ehabkost@redhat.com> In-Reply-To: <1349270954-4657-1-git-send-email-ehabkost@redhat.com> References: <1349270954-4657-1-git-send-email-ehabkost@redhat.com> X-Scanned-By: MIMEDefang 2.68 on 10.5.11.24 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 209.132.183.28 Cc: Igor Mammedov , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Gleb Natapov , Paolo Bonzini Subject: [Qemu-devel] [RFC 18/18] pc: generate APIC IDs according to CPU topology (v3) X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org This keeps compatibility on machine-types pc-1.2 and older, and prints a warning in case the requested configuration won't get the correct topology. At first I was going to use object_property_add() on PC instance_init function, but this wouldn't allow us to use global properties to set it[1]. So I had to use a static DEFINE_PROP_BIT for the contiguous_apic_ids property. [1] See my qdev question at: http://article.gmane.org/gmane.comp.emulators.qemu/173625 Changes v2 -> v3: - Now all code is inside hw/pc.c - Use a real "PC" class and a "contiguous_apic_ids" property Changes v1 -> v2: - Move code to cpu.c - keep using cpu_index on *-user - Use SMP.contiguous_apic_ids global property - Prints warning in case the compatibility mode will expose incorrect topology Signed-off-by: Eduardo Habkost --- hw/pc.c | 45 ++++++++++++++++++++++++++++++++++++++++----- hw/pc_piix.c | 4 ++++ 2 files changed, 44 insertions(+), 5 deletions(-) diff --git a/hw/pc.c b/hw/pc.c index 4c9b2f6..c33768b 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -52,6 +52,8 @@ #include "arch_init.h" #include "bitmap.h" #include "vga-pci.h" +#include "topology.h" +#include "cpus.h" /* debug PC/ISA interrupts */ //#define DEBUG_IRQ @@ -552,13 +554,34 @@ static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val) typedef struct PC { DeviceState parent_obj; + + /* Compatibility mode that force APIC IDs to be contiguous + * + * Setting it to true may break some CPU topologies (e.g. if core or thread + * count is not a power of 2). + */ +#define PC_FLAG_CONTIGUOUS_APIC_IDS 0 + + uint32_t flags; } PC; +static Property pc_properties[] = { + DEFINE_PROP_BIT("contiguous_apic_ids", PC, flags, + PC_FLAG_CONTIGUOUS_APIC_IDS, false), + DEFINE_PROP_END_OF_LIST() +}; + +static void pc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + dc->props = pc_properties; +} + static const TypeInfo pc_type_info = { .name = TYPE_PC_MACHINE, .parent = TYPE_DEVICE, .instance_size = sizeof(PC), - .class_size = sizeof(DeviceClass), + .class_init = pc_class_init, }; static void pc_register_type(void) @@ -576,10 +599,22 @@ type_init(pc_register_type); */ static uint32_t apic_id_for_cpu(PC *pc, int cpu_index) { - /* right now APIC ID == CPU index. this will eventually change to use - * the CPU topology configuration properly - */ - return cpu_index; + unsigned int correct_id; + static bool warned; + bool contig; + + correct_id = topo_apicid_for_cpu(smp_cores, smp_threads, cpu_index); + contig = object_property_get_bool(OBJECT(pc), "contiguous_apic_ids", NULL); + if (contig) { + if (cpu_index != correct_id && !warned) { + fprintf(stderr, "warning: CPU topology in compat mode, " + "results won't match the requested topology\n"); + warned = true; + } + return cpu_index; + } else { + return correct_id; + } } int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) diff --git a/hw/pc_piix.c b/hw/pc_piix.c index f861907..8a4a5f6 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -374,6 +374,10 @@ static QEMUMachine pc_machine_v1_3 = { .driver = "ivshmem",\ .property = "use64",\ .value = "0",\ + },{\ + .driver = "PC",\ + .property = "contiguous_apic_ids",\ + .value = "true",\ } static QEMUMachine pc_machine_v1_2 = {