From patchwork Tue Oct 2 22:45:53 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: [U-Boot,5/7] Tegra30: Cardhu: Add DT files Date: Tue, 02 Oct 2012 12:45:53 -0000 From: Tom Warren X-Patchwork-Id: 188677 Message-Id: <1349217955-8729-6-git-send-email-twarren@nvidia.com> To: u-boot@lists.denx.de Cc: swarren@nvidia.com, Tom Warren , trini@ti.com, twarren.nvidia@gmail.com These are stripped down for bringup, They'll be filled out later to match-up with the kernel DT contents, and/or as devices are brought up (mmc, usb, spi, etc.). Signed-off-by: Tom Warren --- arch/arm/dts/tegra30.dtsi | 30 ++++++++++++++++++++++++++++++ board/nvidia/dts/tegra30-cardhu.dts | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 65 insertions(+), 0 deletions(-) create mode 100644 arch/arm/dts/tegra30.dtsi create mode 100644 board/nvidia/dts/tegra30-cardhu.dts diff --git a/arch/arm/dts/tegra30.dtsi b/arch/arm/dts/tegra30.dtsi new file mode 100644 index 0000000..122c134 --- /dev/null +++ b/arch/arm/dts/tegra30.dtsi @@ -0,0 +1,30 @@ +/include/ "skeleton.dtsi" + +/ { + model = "NVIDIA Tegra30"; + compatible = "nvidia,tegra30"; + + clocks { + #address-cells = <1>; + #size-cells = <0>; + + osc: clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + }; + + gpio: gpio@6000d000 { + compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; + reg = <0x6000d000 0x1000>; + #gpio-cells = <2>; + gpio-controller; + }; + + serial@70006000 { + compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; + reg = <0x70006000 0x40>; + reg-shift = <2>; + status = "disabled"; + }; +}; diff --git a/board/nvidia/dts/tegra30-cardhu.dts b/board/nvidia/dts/tegra30-cardhu.dts new file mode 100644 index 0000000..68563e8 --- /dev/null +++ b/board/nvidia/dts/tegra30-cardhu.dts @@ -0,0 +1,35 @@ +/dts-v1/; + +/memreserve/ 0x1c000000 0x04000000; +/include/ ARCH_CPU_DTS + +/ { + model = "NVIDIA Cardhu"; + compatible = "nvidia,cardhu", "nvidia,tegra30"; + + aliases { + }; + + memory { + device_type = "memory"; + reg = <0x80000000 0xc0000000>; + }; + + clocks { + clk_32k: clk_32k { + clock_frequency = <32000>; + }; + osc { + clock-frequency = <12000000>; + }; + }; + + clock@60006000 { + clocks = <&clk_32k &osc>; + }; + + serial@70006000 { + status = "ok"; + clock-frequency = < 216000000 >; + }; +};