Patchwork [MIPS] Adjust baddu patterns for recent simplify-rtx.c change

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Submitter Richard Sandiford
Date Oct. 2, 2012, 7:37 p.m.
Message ID <877gr8r7g4.fsf@talisman.home>
Download mbox | patch
Permalink /patch/188646/
State New
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Comments

Richard Sandiford - Oct. 2, 2012, 7:37 p.m.
As promised, here's the patch to adjust the MIPS BADDU patterns for
the new (subreg (plus)) simplification.  Tested on mipsisa32-elf
and mipsisa64-elf.  Applied.

Richard


gcc/
	* config/mips/mips.md (*baddu_si_eb, *baddu_si_el): Merge into...
	(*baddu_si): ...this new pattern.

Patch

Index: gcc/config/mips/mips.md
===================================================================
--- gcc/config/mips/mips.md	2012-09-29 16:57:31.000000000 +0100
+++ gcc/config/mips/mips.md	2012-10-01 21:33:39.358480799 +0100
@@ -1293,23 +1293,12 @@  (define_insn_and_split "*addsi3_extended
 
 ;; Combiner patterns for unsigned byte-add.
 
-(define_insn "*baddu_si_eb"
+(define_insn "*baddu_si"
   [(set (match_operand:SI 0 "register_operand" "=d")
         (zero_extend:SI
-	 (subreg:QI
-	  (plus:SI (match_operand:SI 1 "register_operand" "d")
-		   (match_operand:SI 2 "register_operand" "d")) 3)))]
-  "ISA_HAS_BADDU && BYTES_BIG_ENDIAN"
-  "baddu\\t%0,%1,%2"
-  [(set_attr "alu_type" "add")])
-
-(define_insn "*baddu_si_el"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-        (zero_extend:SI
-	 (subreg:QI
-	  (plus:SI (match_operand:SI 1 "register_operand" "d")
-		   (match_operand:SI 2 "register_operand" "d")) 0)))]
-  "ISA_HAS_BADDU && !BYTES_BIG_ENDIAN"
+	 (plus:QI (match_operand:QI 1 "register_operand" "d")
+		  (match_operand:QI 2 "register_operand" "d"))))]
+  "ISA_HAS_BADDU"
   "baddu\\t%0,%1,%2"
   [(set_attr "alu_type" "add")])