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[76.220.57.190]) by mx.google.com with ESMTPS id uq6sm9447293igb.14.2012.10.02.12.35.21 (version=TLSv1/SSLv3 cipher=OTHER); Tue, 02 Oct 2012 12:35:22 -0700 (PDT) Received: by gnu-tools-1.localdomain (Postfix, from userid 1000) id 8F8C01A4D0E; Tue, 2 Oct 2012 12:35:19 -0700 (PDT) Date: Tue, 2 Oct 2012 12:35:19 -0700 From: "H.J. Lu" To: gcc-patches@gcc.gnu.org Cc: Uros Bizjak Subject: PATCH: PR target/54741: Check SSE and YMM state support for -march=native Message-ID: <20121002193519.GA29567@gmail.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch checks SSE and YMM state support for -march=native. Tested on Linux/x86-64. OK to install? Thanks. H.J. --- 2012-10-02 H.J. Lu PR target/54741 * config/i386/driver-i386.c (XCR_XFEATURE_ENABLED_MASK): New. (XSTATE_FP): Likewise. (XSTATE_SSE): Likewise. (XSTATE_YMM): Likewise. (host_detect_local_cpu): Disable AVX, AVX2, FMA, FMA4 and XOP if SSE and YMM states aren't supported. diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index bda4e02..4dffc51 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -390,6 +390,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int has_hle = 0, has_rtm = 0; unsigned int has_rdrnd = 0, has_f16c = 0, has_fsgsbase = 0; unsigned int has_rdseed = 0, has_prfchw = 0, has_adx = 0; + unsigned int has_osxsave = 0; bool arch; @@ -431,6 +432,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_sse4_1 = ecx & bit_SSE4_1; has_sse4_2 = ecx & bit_SSE4_2; has_avx = ecx & bit_AVX; + has_osxsave = ecx & bit_OSXSAVE; has_cmpxchg16b = ecx & bit_CMPXCHG16B; has_movbe = ecx & bit_MOVBE; has_popcnt = ecx & bit_POPCNT; @@ -460,6 +462,26 @@ const char *host_detect_local_cpu (int argc, const char **argv) has_adx = ebx & bit_ADX; } + /* Get XCR_XFEATURE_ENABLED_MASK register with xgetbv. */ +#define XCR_XFEATURE_ENABLED_MASK 0x0 +#define XSTATE_FP 0x1 +#define XSTATE_SSE 0x2 +#define XSTATE_YMM 0x4 + if (has_osxsave) + asm (".byte 0x0f; .byte 0x01; .byte 0xd0" + : "=a" (eax), "=d" (edx) + : "c" (XCR_XFEATURE_ENABLED_MASK)); + + /* Check if SSE and YMM states are supported. */ + if ((eax & (XSTATE_SSE | XSTATE_YMM)) == (XSTATE_SSE | XSTATE_YMM)) + { + has_avx = 0; + has_avx2 = 0; + has_fma = 0; + has_fma4 = 0; + has_xop = 0; + } + /* Check cpuid level of extended features. */ __cpuid (0x80000000, ext_level, ebx, ecx, edx);